On Fri, 9 May 2025 23:29:50 +0900
Chen-Yu Tsai wrote:
> On Fri, May 9, 2025 at 11:14 PM Andre Przywara wrote:
> >
> > On Wed, 7 May 2025 15:19:21 -0500
> > Chris Morgan wrote:
> >
> > Hi,
> >
> > despite the slightly ill fate of this series
On Wed, 7 May 2025 15:19:42 -0500
Chris Morgan wrote:
Hi Chris,
> From: Chris Morgan
>
> The LCD backlight for this device can be exposed as a simple GPIO-
> controlled device. It would be more accurately modelled using PWM to
> enable brightness control, however the PWM driver design for the
gan
>
> Add the required LVDS reset for the LCD TCON. Note that while this
> reset is exposed for the T507, H616, and H700 only the H700 has
> an LCD controller.
>
> Signed-off-by: Chris Morgan
> Signed-off-by: Ryan Walklin
Matches the T507 manual:
Reviewed-by: Andre
On Wed, 7 May 2025 15:19:20 -0500
Chris Morgan wrote:
> From: Chris Morgan
>
> Add the required LVDS reset binding for the LCD TCON.
>
> Signed-off-by: Chris Morgan
> Signed-off-by: Ryan Walklin
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> include/dt-bi
On Thu, 27 Feb 2025 23:43:29 +0100
Ulf Hansson wrote:
Hi Ulf,
sorry for the delay, I actually changed to code according to your comments
back then already, just now find time to come back to this.
> On Fri, 21 Feb 2025 at 02:00, Andre Przywara wrote:
> >
> > The Allwinner Po
On Fri, 21 Feb 2025 19:10:33 +0100
Jernej Škrabec wrote:
> Dne petek, 21. februar 2025 ob 01:57:59 Srednjeevropski standardni čas je
> Andre Przywara napisal(a):
> > The Allwinner Power Reset Clock Management (RPCM) block contains a few
> > bits that control some power
On Mon, 31 Mar 2025 11:32:58 +0100
Steven Price wrote:
> On 27/03/2025 12:36, Andre Przywara wrote:
> > On Thu, 13 Mar 2025 00:23:18 +0100
> > Philippe Simons wrote:
> >
> > Hi Rob, Boris, Steven,
> >
> >> When the GPU is the only device attached
On Mon, 31 Mar 2025 11:32:58 +0100
Steven Price wrote:
Hi Steven,
thanks for having a look!
> On 12/03/2025 23:23, Philippe Simons wrote:
> > Tie the Allwinner compatible string to the two features bits that will
> > toggle the clocks and the reset line whenever the power domain is changing
> >
On Thu, 13 Mar 2025 00:23:18 +0100
Philippe Simons wrote:
Hi Rob, Boris, Steven,
> When the GPU is the only device attached to a single power domain,
> core genpd disable and enable it when gpu enter and leave runtime suspend.
>
> Some power-domain requires a sequence before disabled,
> and the
On Mon, 10 Mar 2025 22:30:36 +1300
"Ryan Walklin" wrote:
Hi Ryan,
> On Tue, 25 Feb 2025, at 6:56 AM, Andre Przywara wrote:
>
> Apologies Andre, I came to review your comments on the TCON series and
> realised I had missed responding to this comment before sending v8.
On Mon, 17 Feb 2025 07:36:22 +1300
Ryan Walklin wrote:
Hi,
> The Allwinner H616 and variants have a new display engine revision
> (DE33).
>
> The mixer configuration registers are significantly different to the DE3
> and DE2 revisions, being split into separate top and display blocks,
> therefo
All Allwinner H616/H618 SoCs contain a Mali G31 MP2 GPU.
Enable the DT nodes for that GPU, and specify the regulator providing
power to the VDD_GPU pins of the package. The rest of the DT node is set
by the SoC, so is not board specific.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts
or anything, so things would need be changed in the generic panfrost
code, where they have the potential of breaking other Mali users.
I would be interested in hearing opinions about this.
Cheers,
Andre
Andre Przywara (5):
dt-bindings: power: Add Allwinner H6/H616 PRCM PPU
pmdomain: sunxi: add H6
perty.
Any board wishing to use the GPU would need to enable the GPU node and
specify the "mali-supply" regulator.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 21 +++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/a
The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali
Bifrost family.
Add the SoC specific compatible string and pair it with the bifrost
fallback compatible.
Signed-off-by: Andre Przywara
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 +
1 file changed, 1
Add a power domain driver for those bits. Some BSP code snippets and
some spare documentation describe three bits, slightly different between
the H6 and H616, so add three power domains for each SoC, connected to
their compatible string.
Signed-off-by: Andre Przywara
---
drivers/pmdomain/
The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power
Reset Clock Management) block that control some power domains.
Those power domains include the one for the GPU, the PLLs and some
analogue circuits.
Signed-off-by: Andre Przywara
---
.../power/allwinner,sun50i-h6-prcm
terface, but then realised that those are
on portD, and we already describe them in this table (above). So those two
were missing all the time.
So having compared these lines to the A133 user manual, I can now say that
they are all correct:
Reviewed-by: Andre Przywara
Linus, in contrast to wh
On Mon, 13 Jan 2025 15:30:24 +0100
Linus Walleij wrote:
> On Fri, Dec 27, 2024 at 12:09 PM Parthiban Nallathambi
> wrote:
>
> > lvds, lcd, dsi all shares the same GPIO D bank and lvds0
> > data 3 lines and lvds1 pins are missed, add them.
> >
> > Signed-off-by: Parthiban Nallathambi
>
> Nob
On Fri, 27 Dec 2024 20:06:30 +0530
Parthiban wrote:
> On 12/27/24 6:30 PM, Parthiban Nallathambi wrote:
> > This series depends on [1] for the eMMC/MMC controller to work and
> > [2] (lined up for 6.14) which adds support for the sram nodes and
> > display engine extends it's usage. Idea of this
On Fri, 27 Dec 2024 18:31:05 +0530
Parthiban Nallathambi wrote:
Hi,
> Display clock uses 1 mixer without rotation support is same
> as v3s. There is also a hidden independent display engine
> with independent tcon_top available in A100/A133 bin (based
> on vendor BSP).
>
> Add new compatible fo
On Fri, 27 Dec 2024 18:30:53 +0530
Parthiban Nallathambi wrote:
Hi,
> A100/A133 uses one mixer without rotation support, which is same
> as sun8i v3s. Add it with fallback to v3s compatible.
>
> Signed-off-by: Parthiban Nallathambi
> ---
> .../devicetree/bindings/clock/allwinner,sun8i-a83t-de
On Fri, 08 Nov 2024 12:40:16 +1100
John Watts wrote:
Hi John,
thanks for taking care and sending a patch!
> On the D1 and T113 the TCON TOP cannot handle setting both DEs to a
> single output, even if the outputs are disabled. As a workaround assign
> DE1 to TVE0 by default.
Can you say *why*
> later commits.
The actual patch looks like a valid transformation to me, so with an
amended commit message:
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Ryan Walklin
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/gpu/drm/sun4i/sun8i_csc.c | 89 ++
On Thu, 20 Jun 2024 23:29:56 +1200
Ryan Walklin wrote:
> The Allwinner H616 and variants have a new display engine revision
> (DE33).
>
> Add display engine bus, clock and mixer bindings for the DE33.
>
> Signed-off-by: Ryan Walklin
> ---
> .../devicetree/bindings/bus/allwinner,sun50i-a64-de2
SIZE; i += 4)
> @@ -534,7 +564,8 @@ static int sun8i_mixer_bind(struct device *dev, struct
> device *master,
> regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
> regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
>
flag to an enum, and refactor the initialiser by
> moving common code to a separate function.
Thanks for splitting this up, makes review much easier.
Can confirm that is just refactoring, from bool to enum:
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Ryan Walklin
Reviewed-by:
krabec
> Signed-off-by: Ryan Walklin
Reviewed-by: Andre Przywara
cheers,
Andre
> ---
> drivers/gpu/drm/sun4i/sun8i_csc.c | 22 +++---
> drivers/gpu/drm/sun4i/sun8i_csc.h | 10 +-
> drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 16 ---
On Fri, 7 Jun 2024 23:00:04 +1200
Ryan Walklin wrote:
Hi Ryan,
> The DE33 is a newer version of the Allwinner Display Engine IP block,
> found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
> supported by the mainline driver.
>
> Notable features (from the H616 datasheet and im
On Fri, 7 Jun 2024 23:00:03 +1200
Ryan Walklin wrote:
Hi Ryan,
thanks for taking the time and posting those patches!
> Buffers, compressed with AFBC, are generally more efficient for memory
> transfers. Add support for them.
>
> Currently it's implemented only for VI layers, but vendor code a
On Mon, 15 Apr 2024 13:00:39 -0300
Maíra Canal wrote:
Hi,
> RPi 0-3 is packed with a GPU that provides 3D rendering capabilities to
> the RPi. Currently, the downstream kernel uses an overlay to enable the
> GPU and use GPU hardware acceleration. When deploying a mainline kernel
> to the RPi 0-3
On Mon, 04 Mar 2024 12:26:46 +0100
"Arnd Bergmann" wrote:
> On Mon, Mar 4, 2024, at 12:24, Andre Przywara wrote:
> > On Mon, 04 Mar 2024 12:11:36 +0100 "Arnd Bergmann" wrote:
> >>
> >> This used to be a 32-bit division. If the rate is never mo
On Mon, 04 Mar 2024 12:11:36 +0100
"Arnd Bergmann" wrote:
Hi,
> On Mon, Mar 4, 2024, at 09:07, Naresh Kamboju wrote:
> > The arm defconfig builds failed on today's Linux next tag next-20240304.
> >
> > Build log:
> > -
> > ERROR: modpost: "__aeabi_uldivmod"
> > [drivers/gpu/drm/sun4i/sun
On Thu, 1 Dec 2022 14:16:04 +0100
Uwe Kleine-König wrote:
Hi Uwe,
> Hello Andre,
>
> On Thu, Dec 01, 2022 at 10:22:52AM +0000, Andre Przywara wrote:
> > Just one comment: I don't see a sunxi specific patch later in the series,
> > though it seems we have at least
larity = PWM_POLARITY_NORMAL;
> @@ -162,6 +162,8 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>
> tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
> state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
> +
> + return 0;
> }
>
> static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
For sunxi:
Reviewed-by: Andre Przywara
Just one comment: I don't see a sunxi specific patch later in the series,
though it seems we have at least one error error exit (see prescaler == 0
above). Plus potentially another exit if clk_get_rate() (at the very
beginning) fails.
Shall I send a patch for that?
Cheers,
Andre.
On Wed, 11 May 2022 13:03:36 +0100
Liviu Dudau wrote:
Hi Liviu,
> On Mon, May 09, 2022 at 02:49:01PM +0100, Andre Przywara wrote:
> > On Fri, 06 May 2022 17:39:53 -0500
> > Rob Herring wrote:
> >
> > > On Fri, 06 May 2022 15:05:32 +0100, Andre Przywara wrote:
e proper name in
the example. The actual property was already documented properly.
Fixes: 2c8b082a3ab1 ("dt-bindings: display: convert Arm Mali-DP to DT schema")
Link:
https://lore.kernel.org/linux-arm-kernel/ynumgeilublhb...@e110455-lin.cambridge.arm.com/
Signed-off-by: Andre Przy
>
> Repair these file references in ARM HDLCD DRM DRIVER, ARM KOMEDA DRM-KMS
> DRIVER and ARM MALI-DP DRM DRIVER.
>
> Signed-off-by: Lukas Bulwahn
Thanks for taking care!
Acked-by: Andre Przywara
Cheers,
Andre
> ---
> Andre, please ack.
> Rob, Krzysztof, please p
On Fri, 06 May 2022 17:39:53 -0500
Rob Herring wrote:
> On Fri, 06 May 2022 15:05:32 +0100, Andre Przywara wrote:
> > The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
> > out a framebuffer and hands the pixels over to a digital signal encoder.
> >
The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
out a framebuffer and hands the pixels over to a digital signal encoder.
It supports multiple layers, scaling and rotation.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../bindings
-by: Andre Przywara
---
.../bindings/display/arm,komeda.txt | 78 ---
.../bindings/display/arm,komeda.yaml | 130 ++
2 files changed, 130 insertions(+), 78 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/arm,komeda.txt
create
The Arm HDLCD is a display controller that scans out a framebuffer and
hands a signal to a digital encoder to generate a DVI or HDMI signal.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/display/arm,hdlcd.txt | 79
y,
because this is used by several DTs in the tree.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/display/arm,pl11x.txt | 110 ---
.../bindings/display/arm,pl11x.yaml | 174 ++
2 files changed, 174 insertions(+), 110 deletions(-)
delete mode 100644 Doc
The Arm HDLCD is a display controller that scans out a framebuffer and
hands a signal to a digital encoder to generate a DVI or HDMI signal.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/display/arm,hdlcd.txt | 79
-by: Andre Przywara
---
.../bindings/display/arm,komeda.txt | 78 ---
.../bindings/display/arm,komeda.yaml | 130 ++
2 files changed, 130 insertions(+), 78 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/arm,komeda.txt
create
The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
out a framebuffer and hands the pixels over to a digital signal encoder.
It supports multiple layers, scaling and rotation.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../bindings
y,
because this is used by several DTs in the tree.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/display/arm,pl11x.txt | 110 ---
.../bindings/display/arm,pl11x.yaml | 174 ++
2 files changed, 174 insertions(+), 110 deletions(-)
delete mode 100644 Doc
On Tue, 25 Jan 2022 12:37:38 +
Liviu Dudau wrote:
Hi,
> On Mon, Jan 24, 2022 at 04:24:37PM +, carsten.haitz...@foss.arm.com wrote:
> > From: Carsten Haitzler
> >
> > Without DRM_GEM_CMA_HELPER HDLCD won't build. This needs to be there too.
> >
> > Fixes: 09717af7d13d ("drm: Remove CON
me.
Since this is a regression introduced with 5.13-rc1, we should merge
this ASAP.
Tested-by: Andre Przywara
Cheers,
Andre
> ---
> v2: Fix building as a module (phy and hdmi are part of the same module, so
> module init callbacks need to be shared)
>
> drivers/gpu
Add the boolean dma-coherent property to the list of allowed properties,
since some boards (Arm Juno) integrate the GPU this way.
Signed-off-by: Andre Przywara
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
Add the boolean dma-coherent property to the list of allowed properties,
since some boards (Arm Juno) integrate the GPU this way.
Signed-off-by: Andre Przywara
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
Date: Mon, 4 May 2020 12:41:55 +0100
Subject: [PATCH 01/16] dt-bindings: mali-midgard: Allow dma-coherent
Add the boolean dma-coherent property to the list of allowed properties,
since some boards (Arm Juno) integrate the GPU this way.
Signed-off-by: Andre Przywara
---
Documentation/devicetree
On Tue, 13 Nov 2018 16:46:33 +0530
Jagan Teki wrote:
Hi,
I couldn't find a schematic for this board, but some things in here
look inconsistent:
> Amarula A64-Relic board by default bound with Techstar TS8550B
> MIPI-DSI panel, add support for it.
>
> DSI panel connected via board DSI port with
On Tue, 13 Nov 2018 16:46:32 +0530
Jagan Teki wrote:
Hi,
> This patch add support for Bananapi S070WV20-CT16 DSI panel to
> BPI-M64 board.
>
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
Are you sure of that? I don't see anything in the schematic to support
this. The
Hi,
On 25/05/18 06:32, Oleksandr Andrushchenko wrote:
> On 05/23/2018 02:46 PM, Juergen Gross wrote:
>> On 23/05/18 13:36, Oleksandr Andrushchenko wrote:
>>> From: Oleksandr Andrushchenko
>>>
>>> Building for a 32-bit target results in warnings from casting
>>> between a 32-bit pointer and a 64-b
On 05/23/2018 17:16, Marek Vasut wrote:
> On 05/18/2018 11:28 AM, Qiang Yu wrote:
>> From: Lima Project Developers
>>
>> Signed-off-by: Qiang Yu
>> Signed-off-by: Neil Armstrong
>> Signed-off-by: Simon Shields
>> Signed-off-by: Heiko Stuebner
>> ---
>> drivers/gpu/drm/Kconfig | 2 ++
>
t;paddr);
^
include/drm/drmP.h:207:34: note: in definition of macro
'DRM_DEBUG_DRIVER'
drm_ut_debug_printk(__func__, fmt, ##args); \
.
Use the proper printk format specifier [1] for dma_addr_t which takes
care of those differences.
Signed-off-by: Andre Przyw
Hi,
On 02/02/16 17:19, Jean-Francois Moine wrote:
> On Wed, 20 Jan 2016 11:14:38 +
> Andre Przywara wrote:
>
>> I haven't looked at it in detail yet, I just tried to compile it for
>> ARM64 to prepare for a test on the Allwinner A64.
>>
>> So just two
Hi Jean-Francois,
I haven't looked at it in detail yet, I just tried to compile it for
ARM64 to prepare for a test on the Allwinner A64.
So just two things I spotted below:
On 15/01/16 15:54, Jean-Francois Moine wrote:
> In recent SoCs, as the H3, Allwinner uses a new display interface, DE2.
> T
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