From: Chaoyi Chen
This series convert cdn-dp-rockchip.txt to yaml.
PATCH 1 try to improve coding style on the existing rk3399 cdn-dp
node.
PATCH 2 try to convert cdn-dp-rockchip.txt to yaml.
Tested with:
1. make ARCH=arm64 dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/dis
From: Chaoyi Chen
Let's make the ports nodes of cdn_dp in the same style as the other
display interface, and match the style of ports's yaml.
Signed-off-by: Chaoyi Chen
---
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
From: Chaoyi Chen
Convert cdn-dp-rockchip.txt to yaml.
Tested with:
1. make ARCH=arm64 dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/rockchip,cdn-dp.yaml
2. make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/roc
Hey there,
On Thu, 1 May 2025 at 12:22, Robert Mader wrote:
> Unlike formats typically used by hardware decoders the 10/12bit formats
> use a LSB alignment. In order to allow fast implementations in GL
> and Vulkan the padding must contain only zeros, so the float
> representation can be calculat
On Fri, May 02, 2025 at 01:32:33PM +0100, Tvrtko Ursulin wrote:
> Hi all,
>
> This is another respin of this old work^1 but this version is a total rewrite
> and completely changes how the control is done.
>
> This time round the work builds upon the "fair" DRM scheduler work I have
> posted
> r
Hi Dave & Sima,
Here goes the drm-intel-gt-next PR towards 6.16. No new features, just fixes.
SLPC wait boost fix for DG1/DG2, engine reset fix for HSW.
Move to usleep_range for <20ms timeouts and fix splats on early probe
errors.
The rest is usual cleanups and improvements to selftests.
Regard
On 23/04/2025 04:46, Abhinav Kumar wrote:
> Hi Krzysztof
>
> On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
>> On 03/12/2024 04:31, Abhinav Kumar wrote:
>>> On some chipsets the display port controller can support more
>>
>> Which chipsets?
>>
>
> From the current list of chipsets which suppo
>
>
> > diff --git a/include/drm/intel/xe_late_bind_mei_interface.h
> b/include/drm/intel/xe_late_bind_mei_interface.h
> > new file mode 100644
> > index ..4005c4c6184f
> > --- /dev/null
> > +++ b/include/drm/intel/xe_late_bind_mei_interface.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License
On Wed, May 07, 2025 at 04:59:12PM -0500, Rob Herring (Arm) wrote:
> The MSM HDMI port nodes are missing any restrictions on additional
> properties. The $ref should be to "/properties/port" rather than
> "/$defs/port-base" as there are not additional properties in the nodes
> to define.
>
> Signe
On Wed, 07 May 2025 09:06:35 -0400 Jeff Layton wrote:
> + * @quarantime_count: max number of entries to be tracked
quarantime
^
:(
--
pw-bot: cr
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks for the feedback! I'll adjust it and give v2 soon.
Thanks,
Wayne
> -Original Message-
> From: Limonciello, Mario
> Sent: Tuesday, May 6, 2025 4:22 AM
> To: Lin, Wayne ; dri-devel@lists.freedesktop.org
> Cc: ville.syrj...@li
On 4/29/2025 9:09 AM, Badal Nilawar wrote:
Load late binding firmware
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_device.c | 2 +
drivers/gpu/drm/xe/xe_late_bind_fw.c | 91 +++-
drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 +
3 files changed, 92 in
On 4/29/2025 9:09 AM, Badal Nilawar wrote:
Search for late binding firmware binaries and populate the meta data of
firmware structures.
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_device.c | 2 +
drivers/gpu/drm/xe/xe_late_bind_fw.c | 101 ++-
d
On Wed, 07 May 2025 16:59:12 -0500, Rob Herring (Arm) wrote:
> The MSM HDMI port nodes are missing any restrictions on additional
> properties. The $ref should be to "/properties/port" rather than
> "/$defs/port-base" as there are not additional properties in the nodes
> to define.
>
> Signed-of
DisplayPort requires per-segment link training when LTTPR are switched
to non-transparent mode, starting with LTTPR closest to the source.
Only when each segment is trained individually, source can link train
to sink.
Implement per-segment link traning when LTTPR(s) are detected, to
support extern
Take into account LTTPR capabilities when selecting maximum allowed
link rate, number of data lines.
Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling")
Reviewed-by: Abel Vesa
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Aleksandrs Vinarskis
Tested-by
Per-segment link training requires knowing the number of LTTPRs
(if any) present. Store the count during LTTPRs' initialization.
Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling")
Reviewed-by: Abel Vesa
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Ale
Recently added Initial LTTPR support in msm/dp has configured LTTPR(s)
to non-transparent mode to enable video output on X1E-based devices
that come with LTTPR on the motherboards. However, video would not work
if additional LTTPR(s) are present between sink and source, which is
the case for USB Ty
Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall
(re)read DPRX caps after LTTPR detection, as required by DP 2.1a,
Section 3.6.7.6.1.
Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling")
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Alek
On 5/8/25 00:24, Dmitry Baryshkov wrote:
On Wed, May 07, 2025 at 10:35:38PM +0300, Vladimir Zapolskiy wrote:
Trivial change, there is a managed device resource version of
of_platform_populate(), and its usage simplifies the code a bit.
Signed-off-by: Vladimir Zapolskiy
---
drivers/gpu/drm/ms
diff --git a/include/drm/intel/xe_late_bind_mei_interface.h
b/include/drm/intel/xe_late_bind_mei_interface.h
new file mode 100644
index ..4005c4c6184f
--- /dev/null
+++ b/include/drm/intel/xe_late_bind_mei_interface.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copy
On Thu, 8 May 2025 at 00:08, Abhinav Kumar wrote:
>
> Hi Alex
>
>
> On 5/7/2025 3:01 PM, Aleksandrs Vinarskis wrote:
> > On Tue, 6 May 2025 at 01:41, Abhinav Kumar
> > wrote:
> >>
> >> Hi Alex
> >>
> >> On 5/4/2025 3:06 PM, Aleksandrs Vinarskis wrote:
> >>> On Sun, 4 May 2025 at 05:02, Abhinav K
On Thu, 8 May 2025 at 08:03, Dave Airlie wrote:
>
> On Thu, 8 May 2025 at 03:52, Johannes Weiner wrote:
> >
> > Hello Dave,
> >
> > On Fri, May 02, 2025 at 01:35:59PM +1000, Dave Airlie wrote:
> > > Hey all,
> > >
> > > This is my second attempt at adding the initial simple memcg/ttm
> > > integr
Hi Alex
On 5/7/2025 3:01 PM, Aleksandrs Vinarskis wrote:
On Tue, 6 May 2025 at 01:41, Abhinav Kumar wrote:
Hi Alex
On 5/4/2025 3:06 PM, Aleksandrs Vinarskis wrote:
On Sun, 4 May 2025 at 05:02, Abhinav Kumar wrote:
Hi Alex
Thanks for the response.
My updates below. I also had one quest
On Wed, May 07, 2025 at 03:49:15PM -0400, Rodrigo Vivi wrote:
> One last thing since I have your attention here. Was any time in the previous
> fwctl discussions talked about the possibility of some extra usages for like
> FW flashing or in-field-repair/tests where big data needs to filled bypassi
On Thu, 8 May 2025 at 03:52, Johannes Weiner wrote:
>
> Hello Dave,
>
> On Fri, May 02, 2025 at 01:35:59PM +1000, Dave Airlie wrote:
> > Hey all,
> >
> > This is my second attempt at adding the initial simple memcg/ttm
> > integration.
> >
> > This varies from the first attempt in two major ways:
On Tue, 6 May 2025 at 01:41, Abhinav Kumar wrote:
>
> Hi Alex
>
> On 5/4/2025 3:06 PM, Aleksandrs Vinarskis wrote:
> > On Sun, 4 May 2025 at 05:02, Abhinav Kumar
> > wrote:
> >>
> >> Hi Alex
> >>
> >> Thanks for the response.
> >>
> >> My updates below. I also had one question for Abel below.
>
The MSM HDMI port nodes are missing any restrictions on additional
properties. The $ref should be to "/properties/port" rather than
"/$defs/port-base" as there are not additional properties in the nodes
to define.
Signed-off-by: Rob Herring (Arm)
---
Documentation/devicetree/bindings/display/msm
On 4/29/2025 9:09 AM, Badal Nilawar wrote:
Introducing late_bind_fw to enable firmware loading for the devices,
such as the fan controller and voltage regulator, during the driver probe.
Typically, firmware for these devices are part of IFWI flash image but
can be replaced at probe after OEM t
On Wed, May 07, 2025 at 10:35:38PM +0300, Vladimir Zapolskiy wrote:
> Trivial change, there is a managed device resource version of
> of_platform_populate(), and its usage simplifies the code a bit.
>
> Signed-off-by: Vladimir Zapolskiy
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 4 +---
> 1 file c
On Wed, May 7, 2025 at 3:22 PM Chris Morgan wrote:
>
> From: Chris Morgan
>
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with the
> LCD
From: Chris Morgan
Add compatible strings for allwinner,sun50i-h616-display-engine. The
device is functionally identical to the
allwinner,sun50i-h6-display-engine.
Signed-off-by: Chris Morgan
---
.../allwinner,sun4i-a10-display-engine.yaml | 39 +++
1 file changed, 22 inserti
From: Chris Morgan
The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.
The DE33 in the H616 has mixer0 and writeback units. The clocks
and resets required are identical to the
From: Chris Morgan
Use the new blender register lookup function where required in the layer
commit and update code.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
---
drivers/gpu/d
From: Chris Morgan
The Allwinner H700 exposes RGB and LVDS pins as well as a HDMI
connector. This requires additional clocks for the TCON_TOP and clock
and resets for the TCON_LCD LCD controllers to be defined as per the
T507 datasheet (which shares the same die).
Signed-off-by: Ryan Walklin
Si
From: Chris Morgan
The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display
pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains
the muxed display pins for RGB and LVDS output support.
Enable the display engine and LCD timing controller, configure the
panel, an
From: Chris Morgan
The LCD backlight for this device can be exposed as a simple GPIO-
controlled device. It would be more accurately modelled using PWM to
enable brightness control, however the PWM driver design for the H616 is
not yet upstreamed.
Add a GPIO backlight node to the DTS.
Signed-of
From: Chris Morgan
The Allwinner H616 and variants have a new display engine revision
(DE33).
The mixer configuration registers are significantly different to the DE3
and DE2 revisions, being split into separate top and display blocks,
therefore a fallback for the mixer compatible is not provide
From: Chris Morgan
The H616 (and related SoC packages sharing the same die) carry the new
DE33 display engine.
Add the mixer configuration and a compatible string for the H616 to the
mixer.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
Changelog v7
From: Chris Morgan
The vi_scaler appears to be used in preference to the ui_scaler module
for hardware video scaling in the DE33.
Enable support for this scaler.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/sun4i/sun8i_ui_layer.c
From: Chris Morgan
The Allwinner H616 has a display pipeline similar to other Allwinner
devices, specifically the A10, but using a newer display engine
revision (DE33).
Not all output pins are exposed on all package variants, for example
only the H700 and T507 have LCD pins exposed, but all vari
From: Chris Morgan
I've spoken with Ryan and he agreed to let me take over this series to
get the display engine working on the Allwinner H616. I've taken his
previous patch series for Display Engine 3.3 and combined it with the
LCD controller patch series. I've also fixed a few additional bugs a
From: Chris Morgan
The Allwinner H616 (and its H618, H700 and T507 package variants with
the same die) have 28 video output pins for RGB/SPI and LVDS display.
These are in GPIO Bank D and are multiplexed.
In RGB mode, pins PD0-PD23 are for 24-bit RGB pixel output, pins
PD24-PD27 are for clock, D
From: Chris Morgan
Add a compatible string for the H616 SRAM C region which is
functionally similar to the A64 SRAM C region.
Signed-off-by: Chris Morgan
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Do
From: Chris Morgan
The Allwinner H616 and variants (H618, H700 and T507) have a new display
engine variant (DE33). Support has been added to the existing DE2/DE3
sun4i driver in a previous patch series (x). The variant is selected via
the appropriate mixer device tree compatible string.
Add the
From: Chris Morgan
The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.
Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output support
Other fea
From: Chris Morgan
Add display engine compatible for the R40 LCD controller, and for the
H616 TV and LCD controller which is functionally identical to the R40.
Signed-off-by: Chris Morgan
---
.../bindings/display/allwinner,sun4i-a10-tcon.yaml | 10 ++
1 file changed, 10 insertions(
From: Chris Morgan
The Allwinner H616 and variants have a new display engine revision
(DE33).
Add a display engine bus binding for the DE33. Note that the DE33
requires 3 register blocks instead of 1. To keep things simple
remove the maxItems value for registers for the child nodes and instead
r
From: Chris Morgan
The Allwinner H616 and related SOCs have an LCD timing controller
(TCON) which is compatible with the R40 SOC's controller and existing
sun4i driver. The H616 does not expose this controller but the H700 and
T507 (based on the same die) do. The controller supports LVDS and RGB
From: Chris Morgan
Add compatible string for allwinner,sun50i-h616-tcon-top with a
fallback string of allwinner,sun50i-h6-tcon-top.
Signed-off-by: Chris Morgan
---
.../display/allwinner,sun8i-r40-tcon-top.yaml | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --gi
From: Chris Morgan
The DE2 and DE3 engines have a blender register range within the
mixer engine register map, whereas the DE33 separates this out into
a separate display group.
Prepare for this by adding a function to look the blender reference up,
with a subsequent patch to add a conditional b
From: Chris Morgan
The Allwinner H616 and variants have a new display engine revision
(DE33).
Add a clock binding for the DE33.
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
Acked-by: Conor Dooley
Reviewed-by: Chen-Yu Tsai
---
Changelog v2..v3:
- Separate content into three patche
From: Chris Morgan
Add the required LVDS reset binding for the LCD TCON.
Signed-off-by: Chris Morgan
Signed-off-by: Ryan Walklin
---
include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h
b/include/dt-bindin
From: Chris Morgan
Add the required LVDS reset for the LCD TCON. Note that while this
reset is exposed for the T507, H616, and H700 only the H700 has
an LCD controller.
Signed-off-by: Chris Morgan
Signed-off-by: Ryan Walklin
---
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
1 file changed, 1
From: Chris Morgan
The Allwinner DE2 and DE3 display engine mixers are currently identified
by a simple boolean flag. This will not scale to support additional DE
variants.
Convert the boolean flag to an enum.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morg
From: Chris Morgan
Now that the DE variant can be selected by enum, take the oppportunity
to factor out some common initialisation code to a separate function.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
Reviewed-by: Andre Przywara
---
Changelog v1..
Hi Lukas,
I wanted to review this series for quite some time but lately have found myself
caught up in quite
a few other things. I've had a look into it last week, but before I delve into
it any further, I was
wondering whether you could take some time to go over the questions and
comments I le
On Wed, May 7, 2025 at 9:45 PM Mario Limonciello wrote:
>
> On 5/7/2025 2:39 PM, Rafael J. Wysocki wrote:
> > On Wed, May 7, 2025 at 9:17 PM Mario Limonciello wrote:
> >>
> >> On 5/7/2025 2:14 PM, Rafael J. Wysocki wrote:
> >>> On Thu, May 1, 2025 at 11:17 PM Mario Limonciello
> >>> wrote:
> >>
On Tue, May 06, 2025 at 03:13:53PM -0300, Jason Gunthorpe wrote:
Hi Jason,
first of all, thank you so much for creating this and for the review here.
> On Tue, Apr 29, 2025 at 09:39:56PM +0530, Badal Nilawar wrote:
>
> > diff --git a/drivers/gpu/drm/xe/xe_pcode_fwctl.c
> > b/drivers/gpu/drm/xe
On Wed, May 7, 2025 at 9:17 PM Mario Limonciello wrote:
>
> On 5/7/2025 2:14 PM, Rafael J. Wysocki wrote:
> > On Thu, May 1, 2025 at 11:17 PM Mario Limonciello
> > wrote:
> >>
> >> From: Mario Limonciello
> >>
> >> commit 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notification
> >> callback
On 5/7/2025 2:39 PM, Rafael J. Wysocki wrote:
On Wed, May 7, 2025 at 9:17 PM Mario Limonciello wrote:
On 5/7/2025 2:14 PM, Rafael J. Wysocki wrote:
On Thu, May 1, 2025 at 11:17 PM Mario Limonciello wrote:
From: Mario Limonciello
commit 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notifi
On Wed, May 07, 2025 at 12:32:49PM -0700, Cavitt, Jonathan wrote:
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, May 7, 2025 12:24 PM
> To: Cavitt, Jonathan
> Cc: intel...@lists.freedesktop.org; Gupta, saurabhg
> ; Zuo, Alex ;
> joonas.lahti...@linux.intel.com; Brost, Ma
On Wed, May 7, 2025 at 3:39 PM Rafael J. Wysocki wrote:
>
> On Wed, May 7, 2025 at 9:17 PM Mario Limonciello wrote:
> >
> > On 5/7/2025 2:14 PM, Rafael J. Wysocki wrote:
> > > On Thu, May 1, 2025 at 11:17 PM Mario Limonciello
> > > wrote:
> > >>
> > >> From: Mario Limonciello
> > >>
> > >> com
Trivial change, there is a managed device resource version of
of_platform_populate(), and its usage simplifies the code a bit.
Signed-off-by: Vladimir Zapolskiy
---
drivers/gpu/drm/msm/msm_mdss.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.
-Original Message-
From: Vivi, Rodrigo
Sent: Wednesday, May 7, 2025 12:24 PM
To: Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; Gupta, saurabhg ;
Zuo, Alex ; joonas.lahti...@linux.intel.com; Brost, Matthew
; Zhang, Jianxun ; Lin,
Shuicheng ; dri-devel@lists.freedesktop.org;
Waj
On Wed, May 07, 2025 at 03:57:26PM +, Jonathan Cavitt wrote:
> Add support for userspace to request a list of observed faults
> from a specified VM.
>
> v2:
> - Only allow querying of failed pagefaults (Matt Brost)
>
> v3:
> - Remove unnecessary size parameter from helper function, as it
>
On Wed, May 07, 2025 at 03:57:24PM +, Jonathan Cavitt wrote:
> Add initial declarations for the drm_xe_vm_get_property ioctl.
>
> v2:
> - Expand kernel docs for drm_xe_vm_get_property (Jianxun)
>
> v3:
> - Remove address type external definitions (Jianxun)
> - Add fault type to xe_drm_fault s
On 5/7/2025 2:14 PM, Rafael J. Wysocki wrote:
On Thu, May 1, 2025 at 11:17 PM Mario Limonciello wrote:
From: Mario Limonciello
commit 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notification
callback support") introduced a VRAM eviction earlier in the PM
sequences when swap was still avail
On Thu, May 1, 2025 at 11:17 PM Mario Limonciello wrote:
>
> From: Mario Limonciello
>
> commit 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notification
> callback support") introduced a VRAM eviction earlier in the PM
> sequences when swap was still available for evicting to. This helped
> to
On 5/7/25 5:47 PM, Rob Clark wrote:
> From: Rob Clark
>
> The driver handles the case where gpu fw is not in the initrd. OTOH it
> doesn't always handle the case where _some_ fw is in the initrd, but
> others are not. In particular the zap fw tends to be signed with an OEM
> specific key, so th
Move the pagefault struct from xe_gt_pagefault.c to the
xe_gt_pagefault_types.h header file, and move the associated enum values
into the regs folder under xe_guc_pagefault_desc.h
Since xe_guc_pagefault_desc.h is being initialized here, also move the
xe_guc_pagefault_desc hardware formats to the n
Add initial declarations for the drm_xe_vm_get_property ioctl.
v2:
- Expand kernel docs for drm_xe_vm_get_property (Jianxun)
v3:
- Remove address type external definitions (Jianxun)
- Add fault type to xe_drm_fault struct (Jianxun)
v4:
- Remove engine class and instance (Ivan)
v5:
- Add declare
Add additional information to each VM so they can report up to the first
50 seen faults. Only pagefaults are saved this way currently, though in
the future, all faults should be tracked by the VM for future reporting.
Additionally, of the pagefaults reported, only failed pagefaults are
saved this
Add additional information to each VM so they can report up to the first
50 seen faults. Only pagefaults are saved this way currently, though in
the future, all faults should be tracked by the VM for future reporting.
Additionally, of the pagefaults reported, only failed pagefaults are
saved this
Add support for userspace to request a list of observed faults
from a specified VM.
v2:
- Only allow querying of failed pagefaults (Matt Brost)
v3:
- Remove unnecessary size parameter from helper function, as it
is a property of the arguments. (jcavitt)
- Remove unnecessary copy_from_user (Jain
The page fault handler should reject write/atomic access to read only
VMAs. Add code to handle this in handle_pagefault after the VMA lookup.
Fixes: 3d420e9fa848 ("drm/xe: Rework GPU page fault handling")
Signed-off-by: Jonathan Cavitt
Suggested-by: Matthew Brost
Reviewed-by: Shuicheng Lin
Rev
On Wed, 7 May 2025 14:01:04 +0100
Adrián Larumbe wrote:
> On 06.05.2025 08:54, Boris Brezillon wrote:
> > On Thu, 24 Apr 2025 03:21:30 +0100
> > Adrián Larumbe wrote:
> >
> > > Unlike in Panthor, from where this change is based on, there is no need
> > > to support tagging of BO's other than U
SoCs like AM62Lx support cut-down version of K3 DSS where although same
register space is supported as in other K3 DSS supported SoCs such as
AM65x, AM62x, AM62Ax but some of the resources such as planes and
corresponding register spaces are truncated.
For e.g. AM62Lx has only single VIDL pipeline
The DSS controller on TI's AM62L SoC is an update from that on TI's
AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is route
This adds support for DSS subsystem present in TI's AM62L SoC
which supports single display pipeline with DPI output which
is also routed to DSI Tx controller within the SoC.
Change Log:
V6:
- Move hw_id indexing logic to skip uninstantiated planes to
internal functions dealing with relevant re
Enable display for AM62L DSS [1] which supports only a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and
the DPI signals from the video
Hello Dave,
On Fri, May 02, 2025 at 01:35:59PM +1000, Dave Airlie wrote:
> Hey all,
>
> This is my second attempt at adding the initial simple memcg/ttm
> integration.
>
> This varies from the first attempt in two major ways:
>
> 1. Instead of using __GFP_ACCOUNT and direct calling kmem charges
On Wed, May 7, 2025 at 7:14 AM Alexei Starovoitov
wrote:
>
> On Tue, May 6, 2025 at 5:10 PM T.J. Mercier wrote:
> >
> > +/**
> > + * get_first_dmabuf - begin iteration through global list of DMA-bufs
> > + *
> > + * Returns the first buffer in the global list of DMA-bufs that's not in
> > the
>
On Wed, May 7, 2025 at 1:15 AM Christian König wrote:
>
> On 5/7/25 02:10, T.J. Mercier wrote:
> > The dmabuf iterator traverses the list of all DMA buffers.
> >
> > DMA buffers are refcounted through their associated struct file. A
> > reference is taken on each buffer as the list is iterated to
On 5/7/25 09:29, Mario Limonciello wrote:
On 5/7/2025 11:15 AM, Lizhi Hou wrote:
The latest userspace runtime allows generating commands which do not
have any argument. Remove the corresponding check in driver IOCTL to
enable this use case.
Signed-off-by: Lizhi Hou
Can the userspace handle
On Wed, 7 May 2025 at 19:43, Rob Clark wrote:
>
> On Sat, May 3, 2025 at 12:17 AM Dmitry Baryshkov
> wrote:
> >
> > There are cases when we want to have separate DRM devices for GPU and
> > display pipelines.
> > One example is development, when it is beneficial to be able to bind the
> > GPU dri
From: "Dr. David Alan Gilbert"
Hi,
A few more AMD deadcoding patches spinning out of the
questions I asked, and Kenneth answered.
See:
https://lore.kernel.org/all/dm4pr12mb5165d85bd85bc8fc8bf7a3b48e...@dm4pr12mb5165.namprd12.prod.outlook.com/
Dave
Signed-off-by: Dr. David Alan Gilbert
From: "Dr. David Alan Gilbert"
smu_v13_0_init_display_count() was added in 2020 by
commit c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)")
but is unused.
See discussion on:
https://lore.kernel.org/all/dm4pr12mb5165d85bd85bc8fc8bf7a3b48e...@dm4pr12mb5165.namprd12.prod.outlook.c
From: "Dr. David Alan Gilbert"
The previous patch removed smu_mode2_reset_is_support()
which was the only function to call through the mode2_reset_is_support()
method pointer.
Remove the remaining functions that were assigned to it
and the pointer itself.
See discussion at:
https://lore.kernel.
From: "Dr. David Alan Gilbert"
smu_mode2_reset_is_support() was added in 2020 by
commit 5c03e5843e6b ("drm/amdgpu:add smu mode1/2 support for aldebaran")
but has remained unused.
See discussion at:
https://lore.kernel.org/all/dm4pr12mb5165d85bd85bc8fc8bf7a3b48e...@dm4pr12mb5165.namprd12.prod.out
-Original Message-
From: Wajdeczko, Michal
Sent: Wednesday, May 7, 2025 9:34 AM
To: Hirschfeld, Dafna ; Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; Gupta, saurabhg ;
Zuo, Alex ; joonas.lahti...@linux.intel.com; Brost, Matthew
; Zhang, Jianxun ; Lin,
Shuicheng ; dri-devel@lis
On Sat, May 3, 2025 at 12:17 AM Dmitry Baryshkov
wrote:
>
> Some of the platforms don't have onboard GPU or don't provide support
> for the GPU in the drm/msm driver. Make it possible to disable the GPU
> part of the driver and build the KMS-only part.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
On Sat, May 3, 2025 at 12:17 AM Dmitry Baryshkov
wrote:
>
> There are cases when we want to have separate DRM devices for GPU and
> display pipelines.
> One example is development, when it is beneficial to be able to bind the
> GPU driver separately, without the display pipeline (and without the
>
On 29.04.2025 16:22, Dafna Hirschfeld wrote:
> On 24.04.2025 20:49, Jonathan Cavitt wrote:
>> Move the pagefault struct from xe_gt_pagefault.c to the
>> xe_gt_pagefault_types.h header file, and move the associated enum values
>> into the regs folder under xe_pagefault_desc.h
>>
>> Since xe_pagef
Hi,
On Fri, May 2, 2025 at 5:11 PM Robin Murphy wrote:
>
> On 02/05/2025 10:59 am, Jens Wiklander wrote:
> > Add tee_shm_alloc_cma_phys_mem() to allocate a physical memory using
> > from the default CMA pool. The memory is represented by a tee_shm object
> > using the new flag TEE_SHM_CMA_BUF to
On 5/7/2025 11:15 AM, Lizhi Hou wrote:
The latest userspace runtime allows generating commands which do not
have any argument. Remove the corresponding check in driver IOCTL to
enable this use case.
Signed-off-by: Lizhi Hou
Can the userspace handle discovery of the difference? Or does this n
From: Vitor Soares
The deprecated UNIVERSAL_DEV_PM_OPS() macro uses the provided callbacks
for both runtime PM and system sleep. This causes the DSI clocks to be
disabled twice: once during runtime suspend and again during system
suspend, resulting in a WARN message from the clock framework when
The latest userspace runtime allows generating commands which do not
have any argument. Remove the corresponding check in driver IOCTL to
enable this use case.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/amdxdna_ctx.c | 22 --
1 file changed, 12 insertions(+), 10 delet
Ignore this one: I misspelt the name of a recipient
-Jonathan Cavitt
-Original Message-
From: Cavitt, Jonathan
Sent: Wednesday, May 7, 2025 8:57 AM
To: intel...@lists.freedesktop.org
Cc: Gupta, saurabhg ; Zuo, Alex ;
Cavitt, Jonathan ; joonas.lahti...@linux.intel.com;
Brost, Matthew ;
Hi Thierry,
> -Original Message-
> From: Thierry Reding
> Sent: 07 May 2025 17:00
> To: Biju Das
> Subject: Re: [PATCH] drm/tegra: rgb: Fix the unbound reference count
>
> On Wed, Feb 05, 2025 at 11:21:35AM +, Biju Das wrote:
> > The of_get_child_by_name() increments the refcount in
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