Hi,
On 5/6/2025 5:41 PM, Lizhi Hou wrote:
>
> On 5/6/25 02:20, Jacek Lawrynowicz wrote:
>> Use FW names from linux-firmware repo instead of deprecated ones.
>>
>> Fixes: c140244f0cfb ("accel/ivpu: Add initial Panther Lake support")
>> Cc: # v6.13+
>> Signed-off-by: Jacek Lawrynowicz
>> ---
>>
[AMD Official Use Only - AMD Internal Distribution Only]
Ping ?
Not picked yet while patches raised before this are merged.
Regards
Sunil Khatri
-Original Message-
From: Koenig, Christian
Sent: Tuesday, April 29, 2025 12:49 PM
To: Khatri, Sunil ; dri-devel@lists.freedesktop.org;
Danil
Ping..
At 2025-04-22 15:59:27, "Andy Yan" wrote:
>
>Hi all,
>
>At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>>> From: Andy Yan
>>>
>>> In some application scenarios, we hope to get the corresponding
>>> connector when the brid
From: Chaoyi Chen
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Tested with RK3399 EVB IND board.
Signed-off-by: Chaoyi Chen
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 163 +
drivers/gpu/drm/r
> Subject: [PATCH 2/3] udmabuf: use sgtable-based scatterlist wrappers
>
> Use common wrappers operating directly on the struct sg_table objects to
> fix incorrect use of statterlists sync calls. dma_sync_sg_for_*()
> functions have to be called with the number of elements originally passed
> to d
Hi Dmitry,
> Subject: Re: [PATCH] drm/virtio: Fix NULL pointer deref in
> virtgpu_dma_buf_free_obj()
>
> On 5/2/25 02:24, Vivek Kasireddy wrote:
> > There is a chance that obj->dma_buf would be NULL by the time
> > virtgpu_dma_buf_free_obj() is called. This can happen for imported
> > prime objec
On 06-05-2025 16:48, Jyothi Kumar Seerapu wrote:
+/**
+ * struct geni_i2c_dev - I2C Geni device specific structure
+ *
+ * @se: geni serial engine
+ * @tx_wm: Tx watermark level
+ * @irq: i2c serial engine interrupt
+ * @err: specifies error codes in i2c transfer failures
+ * @adap: i2c geni a
On 05/07/2025, Luca Ceresoli wrote:
> Hello Liu,
Hi Luca,
>
> thanks for your further feedback.
>
> On Tue, 6 May 2025 10:24:18 +0800
> Liu Ying wrote:
>
>> On 04/30/2025, Luca Ceresoli wrote:
>>> Hello Liu,
>>
>> Hi Luca,
>>
>>>
>>> On Tue, 29 Apr 2025 10:10:55 +0800
>>> Liu Ying wrote:
>
re_clk_rate < adjusted_mode_clk * 1000)
+ return MODE_CLOCK_HIGH;
+
/*
* max crtc width is equal to the max mixer width * 2 and max height is
4K
*/
---
base-commit: db76003ade5953d4a83c2bdc6e15c2d1c33e7350
change-id: 20250506-filter-modes-c60b4332769f
Best regards,
--
Jessica Zhang
From: "Dr. David Alan Gilbert"
The last use of smu_v11_0_get_dpm_level_range() was removed in 2020 by
commit 46a301e14e8a ("drm/amd/powerplay: drop unnecessary Navi1x specific
APIs")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 5 ---
.
Original drm_edid_get_monitor_name encapsulates raw edid in drm_edid and
then call get_monitor_name. AMD still stores the display name for
debugging, but it is migrating to drm_edid, on the other hand,
drm_dp_mst_topology and sil-sii8620 still use the raw edid version.
Split drm_edid_get_monitor_n
From: "Dr. David Alan Gilbert"
Hi,
A bunch more deadcode around the AMD GPUs.
(I've not done smu_v14 which all looks rather new
to me, so perhaps you're still intending to use
some of the unused functions).
Signed-off-by: Dr. David Alan Gilbert
Dr. David Alan Gilbert (3):
drm/amd/pm/smu7:
From: "Dr. David Alan Gilbert"
smu7_copy_bytes_from_smc() was added in 2016 by
commit 1ff55f465103 ("drm/amd/powerplay: implement smu7_smumgr for asics
with smu ip version 7.")
but never used.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
.../drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
From: "Dr. David Alan Gilbert"
smu_v13_0_display_clock_voltage_request() and
smu_v13_0_set_min_deep_sleep_dcefclk() were added in 2020 by
commit c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)")
but have remained unused.
Remove them.
smu_v13_0_display_clock_voltage_request() w
Add Linux opaque object to dc_sink for storing edid data cross driver,
drm_edid. Also include the Linux call to free this object, the
drm_edid_free()
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_edid.c | 7 +++
drivers/gpu/drm/amd/display/amdgpu_dm/dc_edid.h | 1 +
Reduce direct handling of edid data by resorting to drm helpers that
deal with this info inside drm_edid infrastructure.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 +
..
AMD driver has a function used to compare if two edid are the same; this
is useful to some of the link detection algorithms implemented by
amdgpu. Since the amdgpu function can be helpful for other drivers, this
commit abstracts the AMD function to make it available at the DRM level
by wrapping exi
From: Rodrigo Siqueira
Since DC is a shared code, this commit introduces a new file to work as
a mid-layer in DC for the edid manipulation.
Signed-off-by: Rodrigo Siqueira
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 1 +
.../gp
From: Rodrigo Siqueira
As part of the effort of stopping using raw edid, this commit move the
copy of the edid in DC to a dedicated function that will allow the usage
of drm_edid in the next steps.
Signed-off-by: Rodrigo Siqueira
Co-developer--by: Melissa Wen
Signed-off-by: Melissa Wen
---
d
Pass dc_sink to dm_helpers_parse_edid_caps(), since it already contains
edid info. It's a groundwork to get rid of raw edid stored as dc_edid.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 18 +++
There is an opaque obj in Linux/DRM to encapsulate edid data as
`drm_edid`. This obj isn't present in other platforms but we need to
pass it through DC when adding sink. To pass this data without
compromise the independence of DC code, make some DC functions accept
edid data as private options.
Si
drm_edid_connector_update() updates display info, filling ELD with
speaker allocation data in the last step of update_dislay_info(). Our
goal is stopping using raw edid, so we can extract SADB from drm_eld
instead of access raw edid to get audio caps.
Signed-off-by: Melissa Wen
---
.../drm/amd/d
Since [1], we can use drm_edid_product_id to get debug info from
drm_edid instead of directly parsing EDID.
Link:
https://lore.kernel.org/dri-devel/cover.1712655867.git.jani.nik...@intel.com/
[1]
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 15
drm_edid_connector_update() updates display info, filling ELD with audio
info from Short-Audio Descriptors in the last step of
update_dislay_info(). Our goal is stopping using raw edid, so we can
extract SAD from drm_eld instead of access raw edid to get audio caps.
Signed-off-by: Melissa Wen
---
Instead of using driver-specific code, use DRM helpers.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/d
Hi,
Siqueira and I have been working on a solution to reduce the usage of
drm_edid_raw in the AMD display driver, since the current guideline in
the DRM subsystem is to stop handling raw edid data in driver-specific
implementation and use opaque `drm_edid` object with common-code
helpers.
In shor
Groundwork that allocates a temporary drm_edid from raw edid to take
advantage of DRM common-code helpers instead of driver-specific code.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff
Make sure the drm_edid container stored in aconnector is freed when
destroying the aconnector.
Fixes: 48edb2a4 ("drm/amd/display: switch amdgpu_dm_connector to use struct
drm_edid")
Reviewed-by: Mario Limonciello
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
The dmabuf iterator traverses the list of all DMA buffers.
DMA buffers are refcounted through their associated struct file. A
reference is taken on each buffer as the list is iterated to ensure each
buffer persists for the duration of the bpf program execution without
holding the list mutex.
Sign
This open coded iterator allows for more flexibility when creating BPF
programs. It can support output in formats other than text. With an open
coded iterator, a single BPF program can traverse multiple kernel data
structures (now including dmabufs), allowing for more efficient analysis
of kernel d
Use the same test buffers as the traditional iterator and a new BPF map
to verify the test buffers can be found with the open coded dmabuf
iterator.
Signed-off-by: T.J. Mercier
---
.../testing/selftests/bpf/bpf_experimental.h | 5 ++
.../selftests/bpf/prog_tests/dmabuf_iter.c| 52 +
Until CONFIG_DMABUF_SYSFS_STATS was added [1] it was only possible to
perform per-buffer accounting with debugfs which is not suitable for
production environments. Eventually we discovered the overhead with
per-buffer sysfs file creation/removal was significantly impacting
allocation and free times
This test creates a udmabuf, and a dmabuf from the system dmabuf heap,
and uses a BPF program that prints dmabuf metadata with the new
dmabuf_iter to verify they can be found.
Signed-off-by: T.J. Mercier
---
tools/testing/selftests/bpf/config| 3 +
.../selftests/bpf/prog_tests/dmab
Rename the debugfs list and mutex so it's clear they are now usable
without the need for CONFIG_DEBUG_FS. The list will always be populated
to support the creation of a BPF iterator for dmabufs.
Signed-off-by: T.J. Mercier
Reviewed-by: Christian König
---
drivers/dma-buf/dma-buf.c | 40
On Tue, 6 May 2025 at 17:36, Marijn Suijten
wrote:
>
> On 2025-05-06 15:53:48, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov
> >
> > Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove
> > DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove
> > DPU_CTL_SPLIT_DISP
R2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
---
base-commit: 0a00723f4c2d0b273edd0737f236f103164a08eb
change-id: 20250506-dpu-sar2130p-no-split-display-442eb0b85165
Best regards,
I think this patch series is still blocked on these requests. Do you want me
to implement these
suggested changes, or should they be dropped?
@Brost, Matthew and @Wajdeczko, Michal
-Jonathan Cavitt
-Original Message-
From: Cavitt, Jonathan
Sent: Wednesday, April 30, 2025 11:42 AM
To: H
From: Sunil Khatri
[ Upstream commit 76047483fe94414edf409dc498498abf346e22f1 ]
fix the below warning messages:
ttm/ttm_bo.c:1098: warning: Function parameter or struct member 'hit_low' not
described in 'ttm_bo_swapout_walk'
ttm/ttm_bo.c:1098: warning: Function parameter or struct member 'evict
Hello Liu,
thanks for your further feedback.
On Tue, 6 May 2025 10:24:18 +0800
Liu Ying wrote:
> On 04/30/2025, Luca Ceresoli wrote:
> > Hello Liu,
>
> Hi Luca,
>
> >
> > On Tue, 29 Apr 2025 10:10:55 +0800
> > Liu Ying wrote:
> >
> >> Hi,
> >>
> >> On 04/25/2025, Luca Ceresoli wrote:
On Fri, 18 Apr 2025 10:49:55 +0300, Dmitry Baryshkov wrote:
> Add support for the Mobile Display SubSystem (MDSS) device present on
> the Qualcomm SAR2130P platform. The MDSS device is similar to SM8550, it
> features two MIPI DSI controllers, two MIPI DSI PHYs and one DisplayPort
> controller.
>
On 05/05/2025 11:11, Vignesh Raman wrote:
The python-artifacts job has a timeout of 10 minutes, which causes
build failures as it was unable to clone the repository within the
specified limits. Set GIT_DEPTH to 10 to speed up cloning and avoid
build failures due to timeouts when fetching the f
On 05/05/2025 11:11, Vignesh Raman wrote:
The current s3cp stopped working after the migration. Update to the
latest mesa and ci-templates to get s3cp working again and adapt to
recent changes in mesa-ci.
Signed-off-by: Vignesh Raman
Acked-by: Helen Koike
---
v2:
- Uprev mesa and ci
On Tue, Apr 29, 2025 at 09:39:56PM +0530, Badal Nilawar wrote:
> diff --git a/drivers/gpu/drm/xe/xe_pcode_fwctl.c
> b/drivers/gpu/drm/xe/xe_pcode_fwctl.c
> new file mode 100644
I really do prefer it if you can find a way to put the code in
drivers/fwctl instead of in DRM subsystem.
> +static int
Le 06/05/2025 à 11:33, Svyatoslav Ryhel a écrit :
SSD2825 is a cost-effective MIPI Bridge Chip solution targeting mainly
smartphones. It can convert 24bit RGB interface into 4-lane MIPI-DSI
interface to drive display modules of up to 800 x 1366, while supporting
AMOLED, a-si LCD or LTPS panel tec
Hi Dmitry,
> Subject: Re: [RFC PATCH 0/2] Virtio-GPU suspend and resume
>
> On 5/5/25 22:38, Kim, Dongwon wrote:
> >> I tried to apply your kernel patches and then suspend/resume guest
> >> kernel, it doesn't work:
> >>
> >> virtio_gpu_transfer_to_host_2d: no backing storage 2
> >> [ 22.909454]
On Thu, May 01, 2025 at 08:38:15PM -0700, Doug Anderson wrote:
> Hi,
>
> On Thu, May 1, 2025 at 12:48 AM wrote:
> >
> > From: Max Krummenacher
> >
> > The bridge driver currently disables handling the hot plug input and
> > relies on a always connected eDP panel with fixed delays when the
> > pa
On Fri, May 02, 2025 at 05:25:40PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Add a compatible string for the Renesas RZ/V2N SoC variants that include a
> Mali-G31 GPU. These variants share the same restrictions on interrupts,
> clocks, and power domains as the RZ/G2L SoC, so extend the ex
On Sat, 3 May 2025 00:07:59 -0400
Joel Fernandes wrote:
> Add documentation strings, comments and AES mode for completeness
> to the Falcon signatures.
>
> Signed-off-by: Joel Fernandes
> ---
> drivers/gpu/nova-core/falcon.rs | 25 +++--
> 1 file changed, 19 insertions(+),
On Sat, 3 May 2025 00:07:56 -0400
Joel Fernandes wrote:
> Add explanation of fwsec with diagrams. This helps clarify how the
> nova-core falcon boot works.
>
> Signed-off-by: Joel Fernandes
> ---
> Documentation/gpu/nova/core/fwsec.rst | 180
> ++ Documentation/gpu/nova
Dear All,
This patchset fixes the incorrect use of dma_sync_sg_*() calls in
media and related drivers. They are replaced with much safer
dma_sync_sgtable_*() variants, which take care of passing the proper
number of elements for the sync operation.
Best regards
Marek Szyprowski, PhD
Samsung R&D I
Use common wrappers operating directly on the struct sg_table objects to
fix incorrect use of statterlists sync calls. dma_sync_sg_for_*()
functions have to be called with the number of elements originally passed
to dma_map_sg_*() function, not the one returned in sgtable's nents.
Fixes: 1ffe09590
The ternary operator is checking if ret is less than zero inside an
if block that also checks if ret is less than zero. Since the nested
ternary statement is always true then the -EIO return is never
executed and can be removed.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/display/drm_dp_he
To support high-resolution cases that exceed the width limitation of
a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate,
additional pipes are necessary to enable parallel data processing
within the SSPP width constraints and MDP clock rate.
Request 4 mixers and 4 DSCs for high-r
The content of every half of screen is sent out via one interface in
dual-DSI case. The content for every interface is blended by a LM
pair in quad-pipe case, thus a LM pair should not blend any content
that cross the half of screen in this case. Clip plane into pipes per
left and right half screen
Currently, SSPPs are assigned to a maximum of two pipes. However,
quad-pipe usage scenarios require four pipes and involve configuring
two stages. In quad-pipe case, the first two pipes share a set of
mixer configurations and enable multi-rect mode when certain
conditions are met. The same applies
Currently, only 2 pipes are used at most for a plane. A stage structure
describes the configuration for a mixer pair. So only one stage is needed
for current usage cases. The quad-pipe case will be added in future and 2
stages are used in the case. So extend the stage to an array with array
size ST
Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are
supported at most in one encoder. The case of 4 channels per encoder is
to be added. To avoid breaking current WB usage case, use dedicated WB
definition before 4 WB usage case is supported in future.
Signed-off-by: Jun Nie
--
The stage contains configuration for a mixer pair. Currently the plane
supports just one stage and 2 pipes. Quad-pipe support will require
handling 2 stages and 4 pipes at the same time. In preparation for that
add a separate define, PIPES_PER_PLANE, to denote number of pipes that
can be used by th
There are 2 pipes in a drm plane at most currently, while 4 pipes are
required for quad-pipe case. Generalize the handling to pipe pair and
ease handling to another pipe pair later. Store pipes in array with
removing dedicated r_pipe.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
---
dri
Add pipe as trace argument in trace_dpu_crtc_setup_mixer() to ease
converting pipe into pipe array later.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +-
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
interface to 3rd PP instead of the 2nd PP.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 --
1 file changed, 8 insertions(+), 2 deletio
Current code only supports usage cases with one pair of mixers at
most. To support quad-pipe usage case, two pairs of mixers need to
be reserved. The lm_count for all pairs is cleared if a peer
allocation fails in current implementation. Reset the current lm_count
to an even number instead of compl
Currently, only one pair of mixers is supported, so a non-zero counter
value is sufficient to identify the correct mixer within that pair.
However, future implementations may involve multiple mixer pairs. With
the current implementation, all mixers within the second pair would be
incorrectly select
It is more likely that resource allocation may fail in complex usage
case, such as quad-pipe case, than existing usage cases.
A resource type ID is printed on failure in the current implementation,
but the raw ID number is not explicit enough to help easily understand
which resource caused the fail
The capability stored in sblk and pipe_hw_caps is checked only for
SSPP of the first pipe in the pair with current implementation. That
of the 2nd pipe, r_pipe, is not checked and may violate hardware
capability. Move requirement check to dpu_plane_atomic_check_pipe()
for the check of every pipe.
9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 10 +-
11 files changed, 403 insertions(+), 247 deletions(-)
---
base-commit: 227403a8562686275197009528ff9f1b440cb20f
change-id: 20250506-quad-pipe-upstream-a640ddc6b1b6
Best regards,
--
Jun Nie
Some display controller support flexible CRTC and DMA, such as the display
controllers in snapdragon SoCs. CRTC can be implemented with several mixers
in parallel, and plane fetching can be implemented with several DMA under
umberala of a virtual drm plane.
The mixer number is decided per panel re
On 5/6/25 02:20, Jacek Lawrynowicz wrote:
Use FW names from linux-firmware repo instead of deprecated ones.
Fixes: c140244f0cfb ("accel/ivpu: Add initial Panther Lake support")
Cc: # v6.13+
Signed-off-by: Jacek Lawrynowicz
---
drivers/accel/ivpu/ivpu_fw.c | 12 ++--
1 file changed
On Wed, 30 Apr 2025 19:19:08 +0530, Aditya Garg wrote:
> %p4cn was recently removed and replaced by %p4chR in vsprintf. So,
> remove the check for %p4cn from checkpatch.pl.
>
>
Applied, thanks!
[1/1] checkpatch: remove %p4cn
commit: a6c0a91ccb257eaec2aee080df06863ce7601315
Best regards
On 5/6/25 02:13, Jacek Lawrynowicz wrote:
- Fix missing alloc log when drm_gem_handle_create() fails in
drm_vma_node_allow() and open callback is not called
- Add ivpu_bo->ctx_id that enables to log the actual context
id instead of using 0 as default
- Add couple WARNs and errors so we can
On Mon, May 5, 2025 at 6:24 PM Sasha Levin wrote:
>
> From: Alexandre Demers
>
> [ Upstream commit ab23db6d08efdda5d13d01a66c593d0e57f8917f ]
>
> DCE6 was missing soft reset, but it was easily identifiable under radeon.
> This should be it, pretty much as it is done under DCE8 and DCE10.
>
> Sign
On Mon, May 5, 2025 at 6:53 PM Sasha Levin wrote:
>
> From: Alex Deucher
>
> [ Upstream commit 2ed83f2cc41e8f7ced1c0610ec2b0821c5522ed5 ]
>
> Use the value pulled from the vbios just like newer chips.
>
> Reviewed-by: Harry Wentland
> Signed-off-by: Alex Deucher
> Signed-off-by: Sasha Levin
T
On Mon, May 5, 2025 at 7:04 PM Sasha Levin wrote:
>
> From: Alex Deucher
>
> [ Upstream commit 2ed83f2cc41e8f7ced1c0610ec2b0821c5522ed5 ]
>
> Use the value pulled from the vbios just like newer chips.
>
> Reviewed-by: Harry Wentland
> Signed-off-by: Alex Deucher
> Signed-off-by: Sasha Levin
T
On Mon, May 5, 2025 at 7:16 PM Sasha Levin wrote:
>
> From: Charlene Liu
>
> [ Upstream commit 23ef388a84c72b0614a6c10f866ffeac7e807719 ]
>
> [why]
> failed due to cmdtable not created.
> switch atombios cmdtable as default.
>
> Reviewed-by: Alvin Lee
> Signed-off-by: Charlene Liu
> Signed-off-
On Mon, May 5, 2025 at 6:34 PM Sasha Levin wrote:
>
> From: Alex Deucher
>
> [ Upstream commit 2ed83f2cc41e8f7ced1c0610ec2b0821c5522ed5 ]
>
> Use the value pulled from the vbios just like newer chips.
>
> Reviewed-by: Harry Wentland
> Signed-off-by: Alex Deucher
> Signed-off-by: Sasha Levin
T
On Tue, May 06, 2025 at 04:04:45PM +0300, Jani Nikula wrote:
> On Tue, 06 May 2025, Jonathan Gray wrote:
> > On Tue, Nov 05, 2024 at 11:23:36AM +0200, Jani Nikula wrote:
> >> On Sun, 03 Nov 2024, Jonathan Gray wrote:
> >> > intel_pxp_gsccs_is_ready_for_sessions() is gated by CONFIG_DRM_I915_PXP
>
INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .features = CTL_SM8550_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_S
On Mon, May 05, 2025 at 07:41:09PM -0700, Matthew Brost wrote:
> On Sat, May 03, 2025 at 05:59:52PM -0300, Maíra Canal wrote:
> > When the DRM scheduler times out, it's possible that the GPU isn't hung;
> > instead, a job may still be running, and there may be no valid reason to
> > reset the hardw
On 06/05/2025 15:52, Jani Nikula wrote:
On Tue, 06 May 2025, Jocelyn Falempe wrote:
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
---
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff --g
On 06/05/2025 14:38, Maíra Canal wrote:
Hi Tvrtko,
On 06/05/25 10:28, Tvrtko Ursulin wrote:
On 06/05/2025 13:46, Maíra Canal wrote:
Hi Tvrtko,
Thanks for your review!
On 06/05/25 08:49, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
Currently, if we add the assertions pre
On 03/05/2025 21:59, Maíra Canal wrote:
Add a test to submit a single job against a scheduler with the timeout
configured and verify that if the job is still running, the timeout
handler will skip the reset and allow the job to complete.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/schedu
On Thu, May 01, 2025 at 11:25:11AM +, Simon Ser wrote:
> Ah, sorry, I missed this message.
>
> On Monday, April 14th, 2025 at 15:28, Ville Syrjälä
> wrote:
>
> > Should probably add a caveat that this needs to be a sync commit/flip.
> > The way the async flip was specified for atomic explic
On Tue, 06 May 2025, Jocelyn Falempe wrote:
> Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
> and drm_log.
>
> Signed-off-by: Jocelyn Falempe
> ---
> MAINTAINERS | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINER
Hi Tvrtko,
On 06/05/25 10:28, Tvrtko Ursulin wrote:
On 06/05/2025 13:46, Maíra Canal wrote:
Hi Tvrtko,
Thanks for your review!
On 06/05/25 08:49, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
Currently, if we add the assertions presented in this commit to the
mock
schedul
Am 06.05.25 um 15:29 schrieb Jocelyn Falempe:
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
Acked-by: Thomas Zimmermann
---
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff --git a
On Tue, Apr 29, 2025 at 09:25:00AM -0700, John Stultz wrote:
> On Mon, Apr 28, 2025 at 7:52 AM Maxime Ripard wrote:
> > On Fri, Apr 25, 2025 at 12:39:40PM -0700, John Stultz wrote:
> > > To your larger point about policy, I do get the tension that you want
> > > to be able to programmatically deri
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
---
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 38df6b159a3b..df3abdcf1767 100644
--- a/MAINTAINERS
+
On 06/05/2025 13:46, Maíra Canal wrote:
Hi Tvrtko,
Thanks for your review!
On 06/05/25 08:49, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
Currently, if we add the assertions presented in this commit to the mock
scheduler, we will see the following output:
[15:47:08]
On 06/05/2025 13:56, Maíra Canal wrote:
Hi Tvrtko,
Thanks for your review!
On 06/05/25 09:03, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
As more KUnit tests are introduced to evaluate the basic capabilities of
the `timedout_job()` hook, the test suite will continue to in
On Tue, 06 May 2025, Jonathan Gray wrote:
> On Tue, Nov 05, 2024 at 11:23:36AM +0200, Jani Nikula wrote:
>> On Sun, 03 Nov 2024, Jonathan Gray wrote:
>> > intel_pxp_gsccs_is_ready_for_sessions() is gated by CONFIG_DRM_I915_PXP
>> > but called from intel_pxp.c which isn't. Provide a fallback inli
Hi Tvrtko,
Thanks for your review!
On 06/05/25 09:03, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
As more KUnit tests are introduced to evaluate the basic capabilities of
the `timedout_job()` hook, the test suite will continue to increase in
duration. To reduce the overall r
t: 0a00723f4c2d0b273edd0737f236f103164a08eb
change-id: 20250506-dpu-sar2130p-no-split-display-442eb0b85165
Best regards,
--
Dmitry Baryshkov
On Tue, Nov 05, 2024 at 11:23:36AM +0200, Jani Nikula wrote:
> On Sun, 03 Nov 2024, Jonathan Gray wrote:
> > intel_pxp_gsccs_is_ready_for_sessions() is gated by CONFIG_DRM_I915_PXP
> > but called from intel_pxp.c which isn't. Provide a fallback inline
> > function to fix the non-optimised build.
On Mon, May 05, 2025 at 04:28:17PM -0700, Jessica Zhang wrote:
>
>
> On 4/24/2025 2:30 AM, Dmitry Baryshkov wrote:
> > Some time ago we started the process of converting HW blocks to use
> > revision-based checks instead of having feature bits (which are easy to
> > miss or to set incorrectly). T
Hi Tvrtko,
Thanks for your review!
On 06/05/25 08:49, Tvrtko Ursulin wrote:
On 03/05/2025 21:59, Maíra Canal wrote:
Currently, if we add the assertions presented in this commit to the mock
scheduler, we will see the following output:
[15:47:08] == [PASSED] drm_sched_basic_tests =
On 06/05/2025 13:59, Dmitry Baryshkov wrote:
On Mon, 05 May 2025 12:02:56 -0500, Kevin Baker wrote:
Switch to panel timings based on datasheet for the AUO G101EVN01.0
LVDS panel. Default timings were tested on the panel.
Previous mode-based timings resulted in horizontal display shift.
Appl
Hi,
On Mon, 05 May 2025 12:02:56 -0500, Kevin Baker wrote:
> Switch to panel timings based on datasheet for the AUO G101EVN01.0
> LVDS panel. Default timings were tested on the panel.
>
> Previous mode-based timings resulted in horizontal display shift.
>
>
Thanks, Applied to https://gitlab.fr
On Tue, May 06, 2025 at 05:42:50PM +0530, Ayushi Makhija wrote:
> Hi Dmitry,
>
> On 5/5/2025 3:32 PM, Dmitry Baryshkov wrote:
> > On Mon, May 05, 2025 at 03:12:41PM +0530, Ayushi Makhija wrote:
> >> Add anx7625 DSI to DP bridge device nodes.
> >>
> >> Signed-off-by: Ayushi Makhija
> >> Reviewed-b
Hi Dmitry,
On 5/5/2025 3:32 PM, Dmitry Baryshkov wrote:
> On Mon, May 05, 2025 at 03:12:41PM +0530, Ayushi Makhija wrote:
>> Add anx7625 DSI to DP bridge device nodes.
>>
>> Signed-off-by: Ayushi Makhija
>> Reviewed-by: Konrad Dybcio
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 183 ++
On 5/6/25 11:47, oushixiong1...@163.com wrote:
> From: Shixiong Ou
>
> [WHY]
> 1. Drivers using DRM_GEM_SHADOW_PLANE_HELPER_FUNCS and
>DRM_GEM_SHMEM_DRIVER_OPS (e.g., udl, ast) do not require
>sg_table import.
>They only need dma_buf_vmap() to access the shared buffer's
>kernel vi
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