On Wed, Apr 30, 2025 at 11:02:14AM +0300, Dan Carpenter wrote:
> Unlock and reschedule if drm_mode_duplicate() fails. In real life, the
> drm_mode_duplicate() function does a small allocation and those never
> fail in current kernels. So this doesn't really affect runtime but
> the missing unlock
Add documentation strings, comments and AES mode for completeness
to the Falcon signatures.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/falcon.rs | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/g
Instances of the Falcon microcontroller appear in modern Nvidia GPUs and
are crucial to the GPU boot process. Document some concepts which will
make nova-core boot code easier to digest. All the information is
derived from public sources such as public documents, OpenRM and Nouveau
code.
Signed-of
Hello,
Please find attached initial documentation for nova-core mainly about the vbios
and boot process. It helps build an understanding of the boot code. All the
information is derived from publicly available code and sources.
This series is based on Alex's v2 patches + nova-next:
https://lore.k
devinit is mentioned in the code. This patch explains it so it is clear
what it does. devinit is not only essential at boot-time, but also at
runtime due to suspend-resume and things like re-clocking.
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/devinit.rst | 59
sysmembar is a critical operation that the GSP falcon needs to perform
in the reset sequence. Add some code comments to clarify.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/gpu.rs | 12 +---
drivers/gpu/nova-core/regs.rs | 2 ++
2 files changed, 11 insertions(+), 3 deletion
Add explanation of fwsec with diagrams. This helps clarify how the
nova-core falcon boot works.
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/fwsec.rst | 180 ++
Documentation/gpu/nova/index.rst | 1 +
2 files changed, 181 insertions(+)
create mode
Add detailed explanation and block diagrams of the layout of the vBIOS
on Nvidia GPUs. This is important to understand how nova-core boots an
Nvidia GPU.
[ Applied Timur Tabi's feedback on providing link to BIT documentation. ]
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/vbios
Add several code comments to reduce acronym soup and explain how devinit magic
and bootflow works before driver loads. These are essential for debug and
development of the nova driver.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/devinit.rs | 34
drive
On Wed, 30 Apr 2025 10:28:48 +0200, Heiko Stuebner wrote:
> Working on an upcoming board dts, I noticed a dtc check warning
> about the port node and at the same time the kernel-test-robot
> noticed the same warning with a overlay I added recently.
>
> So allow the port node in the binding of tw
On Fri, May 02, 2025 at 04:01:35PM -0700, Jessica Zhang wrote:
>
>
> On 5/2/2025 2:54 PM, Dmitry Baryshkov wrote:
> > On Fri, May 02, 2025 at 10:41:41AM -0700, Jessica Zhang wrote:
> > >
> > >
> > > On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
> > > > Initialize LTTPR before msm_dp_panel_r
On 5/2/2025 9:59 PM, Alexandre Courbot wrote:
>> pub trait AlignUp {
>> fn align_up(self, alignment: Self) -> Self;
>> }
>>
>> macro_rules! align_up_impl {
>> ($($t:ty),+) => {
>> $(
>> impl AlignUp for $t {
>> fn align_up(self, alignment: Self) -> Sel
Hi Dave,
kernel test robot noticed the following build errors:
[auto build test ERROR on tj-cgroup/for-next]
[also build test ERROR on akpm-mm/mm-everything linus/master v6.15-rc4]
[cannot apply to drm-misc/drm-misc-next drm-tip/drm-tip next-20250502]
[If your patch is applied to the wrong git
On Sat May 3, 2025 at 4:59 AM JST, Joel Fernandes wrote:
> Hello, Alex,
>
> On 5/2/2025 12:57 AM, Alexandre Courbot wrote:
>> On Thu May 1, 2025 at 9:58 PM JST, Alexandre Courbot wrote:
>>> From: Joel Fernandes
>>>
>>> This will be used in the nova-core driver where we need to upward-align
>>> the
Hi,
Thanks for fixing this.
However, I think checkpatch reports some warnings, including spacing
warning and a mismatch author name vs SOB as below. Once they are fixed
in V2 I will send them to test.
$ ./scripts/checkpatch.pl
drm-amd-display-dc-irq-Remove-duplications-of-hpd_ack-function-f
On 5/2/2025 2:54 PM, Dmitry Baryshkov wrote:
On Fri, May 02, 2025 at 10:41:41AM -0700, Jessica Zhang wrote:
On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall
(re)read DPRX caps after LTTPR detection, as required by DP 2.1,
On Wed, Apr 30, 2025 at 03:00:49PM +0200, Krzysztof Kozlowski wrote:
> Add support for DSI on Qualcomm SM8750 SoC with notable difference:
>
> DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> parents before DSI PHY is configured, the PLLs are prepared and their
> initial rat
On Wed, Apr 30, 2025 at 03:00:47PM +0200, Krzysztof Kozlowski wrote:
> Driver unconditionally saves current state on first init in
> dsi_pll_7nm_init(), but does not save the VCO rate, only some of the
> divider registers. The state is then restored during probe/enable via
> msm_dsi_phy_enable() -
On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
> masks and shifts and make the code a bit more readable.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes in v5:
> 1. New patch
> ---
> drivers/
On Wed, Apr 30, 2025 at 03:00:44PM +0200, Krzysztof Kozlowski wrote:
> According to Hardware Programming Guide for DSI PHY, the retime buffer
> resync should be done after PLL clock users (byte_clk and intf_byte_clk)
> are enabled. Downstream also does it as part of configuring the PLL.
>
> Drive
On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote:
> On SM8750 the setting rate of pixel and byte clocks, while the parent
> DSI PHY PLL, fails with:
>
> disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
>
> DSI PHY PLL has to be unprepared and its "PLL Power Do
Hi James,
checkpatch reports the following warning and error
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit
description?)
#18:
Adds a kernel-doc for externally linked dc_stream_remove_writeback()
function.
ERROR: trailing whitespace
#39: FILE: drivers/gpu/drm/amd/dis
The pull request you sent on Sat, 3 May 2025 06:13:49 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2025-05-03
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/6de6674c66bce543c6ae62f49eb35a1ab9bb7425
Thank you!
--
Deet-doot-dot, I am a bot.
ht
On Fri, May 02, 2025 at 10:41:41AM -0700, Jessica Zhang wrote:
>
>
> On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
> > Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall
> > (re)read DPRX caps after LTTPR detection, as required by DP 2.1,
> > Section 3.6.7.6.1.
> >
> > Fixes:
On Tue, 22 Apr 2025 12:59:43 +0300, Dafna Hirschfeld wrote:
> the pages pointer is not used, remove it
>
>
Applied to drm-misc-next, thanks!
[1/1] drm/gpusvm: remove unused pages pointer
commit: a912b0c8b5eabd9b70dc24cc97a167eb7287a20a
Best regards,
--
Lucas De Marchi
Marcus Folkesson writes:
Hello Marcus,
> Hello Javier,
> On Mon, Apr 28, 2025 at 09:16:32AM +0200, Javier Martinez Canillas wrote:
>> Marcus Folkesson writes:
>>
>> Hello Marcus,
>>
>> > We start to have support many Sitronix displays in the tiny directory,
>> > and we expect more to come.
>>
On Thu, 2025-05-01 at 21:58 +0900, Alexandre Courbot wrote:
> +pub(crate) const FIRMWARE_VERSION: &str = "535.113.01";
This needs to change to 570.144. You can find images to use here:
https://github.com/NVIDIA/linux-firmware/commits/nvidia-staging/
Hi Linus,
Weekly drm fixes, amdgpu and xe as usual, the new adp driver has a
bunch of vblank fixes, then a bunch of small fixes across the board.
Seems about the right level for this time in the release cycle.
Regards,
Dave.
drm-fixes-2025-05-03:
drm fixes for 6.15-rc5
ttm:
- docs warning fix
Hello, Alex,
On 5/2/2025 12:57 AM, Alexandre Courbot wrote:
> On Thu May 1, 2025 at 9:58 PM JST, Alexandre Courbot wrote:
>> From: Joel Fernandes
>>
>> This will be used in the nova-core driver where we need to upward-align
>> the image size to get to the next image in the VBIOS ROM.
>>
>> [acour
Hi,
On 30/04/25 17:51, Maíra Canal wrote:
When a CL/CSD job times out, we check if the GPU has made any progress
since the last timeout. If so, instead of resetting the hardware, we skip
the reset and let the timer get rearmed. This gives long-running jobs a
chance to complete.
However, when `t
On 02-05-2025 22:26, Rob Clark wrote:
In situations where mapping/unmapping squence can be controlled by
typo squence -> sequence
userspace, attempting to map over a region that has not yet been
unmapped is an error. But not something that should spam dmesg.
Now that there is a quirk, we
Hi Dave, Simona,
New stuff for 6.16. Lots of new stuff. The main one is user queues for gfx
11 and 12.
The following changes since commit dce8bd9137b88735dd0efc4e2693213d98c15913:
drm/amdgpu/gfx12: fix num_mec (2025-03-26 17:47:18 -0400)
are available in the Git repository at:
https://gi
On 2025-04-25 23:02, Konrad Dybcio wrote:
On 4/25/25 10:22 PM, barnabas.cze...@mainlining.org wrote:
On 2025-04-25 21:26, Konrad Dybcio wrote:
On 4/25/25 5:13 PM, barnabas.cze...@mainlining.org wrote:
On 2025-04-25 11:57, Konrad Dybcio wrote:
On 4/23/25 4:46 PM, barnabas.cze...@mainlining.org
On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall
(re)read DPRX caps after LTTPR detection, as required by DP 2.1,
Section 3.6.7.6.1.
Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling")
Reviewed-by: Dmitry Bary
From: Rob Clark
If userspace has opted-in to VM_BIND, then GPU hangs and VM_BIND errors
will mark the VM as unusable.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h| 17 +
drivers/gpu/drm/msm/msm_gem_submit.c | 3 +++
drivers/gpu/drm/msm/msm_gpu.c|
From: Rob Clark
In this case, userspace could request dumping partial GEM obj mappings.
Also drop use of should_dump() helper, which really only makes sense in
the old submit->bos[] table world.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu.c | 17 ++---
1 file changed,
From: Rob Clark
Buffers that are not shared between contexts can share a single resv
object. This way drm_gpuvm will not track them as external objects, and
submit-time validating overhead will be O(1) for all N non-shared BOs,
instead of O(n).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm
From: Rob Clark
Add a SET_PARAM for userspace to request to manage to the VM itself,
instead of getting a kernel managed VM.
In order to transition to a userspace managed VM, this param must be set
before any mappings are created.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_g
From: Rob Clark
In the next commit, a way for userspace to opt-in to userspace managed
VM is added. For this to work, we need to defer creation of the VM
until it is needed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.c
From: Rob Clark
This is a more descriptive name.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 4 ++--
drivers/gpu/drm/msm/msm_gem.h | 2 +-
drivers/gpu/drm/msm/msm_gem_vma.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_g
From: Rob Clark
Add PRR (Partial Resident Region) is a bypass address which make GPU
writes go to /dev/null and reads return zero. This is used to implement
vulkan sparse residency.
To support PRR/NULL mappings, we allocate a page to reserve a physical
address which we know will not be used as
From: Rob Clark
Only needs to be supported for iopgtables mmu, the other cases are
either only used for kernel managed mappings (where offset is always
zero) or devices which do not support sparse bindings.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpummu.c | 5 -
drive
From: Rob Clark
Most of the driver code doesn't need to reach in to msm specific fields,
so just use the drm_gpuvm/drm_gpuva types directly. This should
hopefully improve commonality with other drivers and make the code
easier to understand.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/ad
From: Rob Clark
We'll re-use this in the vm_bind path.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 12 ++--
drivers/gpu/drm/msm/msm_gem.h | 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem
From: Rob Clark
Convert to using the gpuvm's r_obj for serializing access to the VM.
This way we can use the drm_exec helper for dealing with deadlock
detection and backoff.
This will let us deal with upcoming locking order conflicts with the
VM_BIND implmentation (ie. in some scenarious we need
From: Rob Clark
Now that we've dropped vram carveout support, we can collapse vma
allocation and initialization. This better matches how things work
with drm_gpuvm.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 30 +++---
drivers/gpu/drm/msm/msm_gem.h
From: Rob Clark
Now that we've realigned deletion and allocation, switch over to using
drm_gpuvm/drm_gpuva. This allows us to support multiple VMAs per BO per
VM, to allow mapping different parts of a single BO at different virtual
addresses, which is a key requirement for sparse/VM_BIND.
This
From: Rob Clark
Previously we'd also tear down the VMA, making the address space
available again. But with drm_gpuvm conversion, this would require
holding the locks of all VMs the GEM object is mapped in. Which is
problematic for the shrinker.
Instead just let the VMA hang around until the GE
From: Rob Clark
This fits better drm_gpuvm/drm_gpuva.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 16 +++-
drivers/gpu/drm/msm/msm_gem_vma.c | 2 ++
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm
From: Rob Clark
It is standing in the way of drm_gpuvm / VM_BIND support. Not to
mention frequently broken and rarely tested. And I think only needed
for a 10yr old not quite upstream SoC (msm8974).
Maybe we can add support back in later, but I'm doubtful.
Signed-off-by: Rob Clark
---
drive
From: Rob Clark
Re-aligning naming to better match drm_gpuvm terminology will make
things less confusing at the end of the drm_gpuvm conversion.
This is just rename churn, no functional change.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Rob Clark
---
drivers/gpu/d
From: Rob Clark
Just some tidying up.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu.h | 44 +++
1 file changed, 29 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/dr
From: Rob Clark
This is a more descriptive name.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 +--
drivers/g
From: Rob Clark
In situations where mapping/unmapping squence can be controlled by
userspace, attempting to map over a region that has not yet been
unmapped is an error. But not something that should spam dmesg.
Now that there is a quirk, we can also drop the selftest_running
flag, and use the
From: Rob Clark
Eases migration for drivers where VAs don't hold hard references to
their associated BO, avoiding reference loops.
In particular, msm uses soft references to optimistically keep around
mappings until the BO is distroyed. Which obviously won't work if the
VA (the mapping) is hold
From: Rob Clark
See commit a414fe3a2129 ("drm/msm/gem: Drop obj lock in
msm_gem_free_object()") for justification.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_gpuvm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/d
From: Rob Clark
Conversion to DRM GPU VA Manager[1], and adding support for Vulkan Sparse
Memory[2] in the form of:
1. A new VM_BIND submitqueue type for executing VM MSM_SUBMIT_BO_OP_MAP/
MAP_NULL/UNMAP commands
2. A new VM_BIND ioctl to allow submitting batches of one or more
MAP/MAP_NU
On 5/1/2025 4:17 PM, Mario Limonciello wrote:
From: Mario Limonciello
Suspend and hibernate notifications are available specifically when
the sequence starts and finishes. However there are no notifications
during the process when tasks have been frozen.
Introduce two new events `PM_SUSPEND_P
From: Lad Prabhakar
Add a compatible string for the Renesas RZ/V2N SoC variants that include a
Mali-G31 GPU. These variants share the same restrictions on interrupts,
clocks, and power domains as the RZ/G2L SoC, so extend the existing schema
validation accordingly.
Signed-off-by: Lad Prabhakar
Hi Laurent,
On Fri, May 02, 2025 at 07:16:57PM +0300, Laurent Pinchart wrote:
> Hi Tommaso,
>
> On Fri, May 02, 2025 at 10:21:21AM +0200, Tommaso Merciai wrote:
> > On Wed, Apr 30, 2025 at 02:28:55AM +0300, Laurent Pinchart wrote:
> > > Hello,
> > >
> > > This patch series extends the VSP1 drive
Hi Tommaso,
On Fri, May 02, 2025 at 10:21:21AM +0200, Tommaso Merciai wrote:
> On Wed, Apr 30, 2025 at 02:28:55AM +0300, Laurent Pinchart wrote:
> > Hello,
> >
> > This patch series extends the VSP1 driver with colorspace support. It
> > turns out that the VSP RPF and WPF entities can convert bet
On Fri, May 02, 2025 at 11:59:23AM +0200, Jens Wiklander wrote:
> Export the two functions cma_alloc() and cma_release().
Why? This is clearly part of a larger series, but you've given those of
us who are subscribed to linux-mm absolutely no information about why
you want to do this.
rnel.org/r/20250430085658.540746-2-oushixiong1025%40163.com
patch subject: [PATCH 2/3] drm/prime: Support importing DMA-BUF without sg_table
config: arc-randconfig-002-20250501
(https://download.01.org/0day-ci/archive/20250502/20250504.fcdq8tcb-...@intel.com/config)
compiler: arc-linux-gcc (G
On 02/05/2025 10:59 am, Jens Wiklander wrote:
Add tee_shm_alloc_cma_phys_mem() to allocate a physical memory using
from the default CMA pool. The memory is represented by a tee_shm object
using the new flag TEE_SHM_CMA_BUF to identify it as physical memory
from CMA.
If and when it's possible to
On 5/1/25 23:17, Mario Limonciello wrote:
> From: Mario Limonciello
>
> As part of the suspend and hibernate sequences devices supported
> by amdgpu will have VRAM evicted. This has been littered with problems
> in the past, and now it is called strategically at multiple times
> during power man
This adds support for using SN65DSI84 in single-link mode with output to
LVDS Channel B.
Signed-off-by: Esben Haabendal
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 34 +++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn6
Hi Dave,
kernel test robot noticed the following build errors:
[auto build test ERROR on tj-cgroup/for-next]
[also build test ERROR on akpm-mm/mm-everything linus/master v6.15-rc4]
[cannot apply to next-20250502]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
On Mon, Apr 14, 2025 at 07:47:26PM +0300, Avizrat, Yaron wrote:
> On 14/04/2025 13:07, Andy Shevchenko wrote:
> > On Sun, Mar 30, 2025 at 02:15:50PM +0300, Avizrat, Yaron wrote:
> >> On 26/03/2025 11:55, Jani Nikula wrote:
> >>> On Wed, 26 Mar 2025, Andy Shevchenko
> >>> wrote:
> +Cc: Jani (
On 5/1/25 11:36 PM, Dave Airlie wrote:
From: Dave Airlie
This adds the memcg object for any user allocated object,
and adds account_op to necessary paths which might populate
a tt object.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++-
drivers/gpu/dr
On 02/05/2025 10:59 am, Jens Wiklander wrote:
Implement DMA heap for protected DMA-buf allocation in the TEE
subsystem.
Restricted memory refers to memory buffers behind a hardware enforced
firewall. It is not accessible to the kernel during normal circumstances
but rather only accessible to cer
On 02/05/2025 10:59 am, Jens Wiklander wrote:
If a parent device is supplied to tee_device_alloc(), copy the dma_mask
field into the new device. This avoids future warnings when mapping a
DMA-buf for the device.
That also sounds dodgy. If the parent device is the hardware device
physically per
On Thu, May 01, 2025 at 03:22:25PM +0300, Raag Jadav wrote:
> On Wed, Apr 09, 2025 at 09:24:41AM +0300, Raag Jadav wrote:
> > On Wed, Apr 09, 2025 at 09:46:33AM +0800, jiangf...@kylinos.cn wrote:
> > > From: Feng Jiang
> > >
> > > When calling scnprintf() to append recovery method to event_string
On Wed 2025-04-30 19:19:08, Aditya Garg wrote:
> %p4cn was recently removed and replaced by %p4chR in vsprintf. So,
> remove the check for %p4cn from checkpatch.pl.
>
> Fixes: 37eed892cc5f ("vsprintf: Use %p4chR instead of %p4cn for reading data
> in reversed host ordering")
> Signed-off-by: Adit
On 5/2/25 15:00, Thomas Hellström wrote:
> The abstraction was previously added to support separate
> ttm_backup implementations.
>
> However with the current implementation casting from a
> struct file to a struct ttm_backup, we run into trouble since
> struct file may have randomized the layout
On 02/05/2025 10:59 am, Jens Wiklander wrote:
Export the global variable dma_contiguous_default_area so
dev_get_cma_area() can be called a module.
What dma_map_ops implementation is in a module? Without any other
context, I can't help thinking this smells of something sketchy.
Thanks,
Robin.
The abstraction was previously added to support separate
ttm_backup implementations.
However with the current implementation casting from a
struct file to a struct ttm_backup, we run into trouble since
struct file may have randomized the layout and gcc complains.
Remove the struct ttm_backup abst
The docs were not properly updated from an earlier version of the code.
Fixes: e7b5d23e5d47 ("drm/ttm: Provide a shmem backup implementation")
Cc: Christian König
Cc: Matthew Brost
Cc: Matthew Auld
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/ttm/ttm
If the new fair policy is at least as good as FIFO and we can afford to
remove round-robin, we can simplify the scheduler code by making the
scheduler to run queue relationship always 1:1 and remove some code.
Also, now that the FIFO policy is gone the tree of entities is not a FIFO
tree any more
To enable drivers which use the scheduler to easily connect with the DRM
cgroup controller we a add a helper to be used for registering for
scheduling weight notifications.
The scheduler itself straightforwardly "connects" with the concept of
scheduling weights, courtesy of the vruntime based desi
Connect the driver to the DRM scheduling cgroup controller by using the
appropriate DRM scheduler helpers.
First part is tracking the scheduling entities belonging to clients and
second is to register the weight change notification helper in the driver
specific struct drm_cgroup_ops.
Signed-off-b
From: Tvrtko Ursulin
Similar to CPU and IO scheduling, implement a concept of weight in the DRM
cgroup controller.
Individual drivers are now able to register with the controller which will
notify them of the relative scheduling weight for each open DRM client.
The notifications are triggered o
To enable adding DRM cgroup support to the DRM scheduler we need a way for
updating the relative scheduling weights per entity at the point the
controller invokes a call-back notifying the driver of a new relative
scheduling weight for a client.
We add two helpers which will allow drivers to opt-i
From: Tvrtko Ursulin
Add a new callback via which the drm cgroup controller will be notifying
clients about their scheduling weight.
At the same time, in order to reduce the amount of tracking with drivers
which will not support any sort of control from the drm cgroup controller
side, lets expre
Lets move all the code dealing with struct drm_sched_rq into a separate
compilation unit. Advantage being sched_main.c is left with a clearer set
of responsibilities.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/
From: Tvrtko Ursulin
To enable propagation of settings from the cgroup DRM controller to DRM
and vice-versa, we need to start tracking to which cgroups DRM clients
belong.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/drm_file.c | 8 +
include/drm/drm_file.h | 6
include/lin
There is no reason to queue just a single job if scheduler can take more
and re-queue the worker to queue more. We can simply feed the hardware
with as much as it can take in one go and hopefully win some latency.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthe
Now that the run queue to scheduler relationship is always 1:1 we can
embed it (the run queue) directly in the scheduler struct and save on
some allocation error handling code and such.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
From: Tvrtko Ursulin
Skeleton controller without any functionality.
Signed-off-by: Tvrtko Ursulin
---
include/linux/cgroup_drm.h| 7 +
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 5 +++
kernel/cgroup/Makefile| 1 +
kernel/cgroup/drm.c |
There is no need to keep entities with no jobs in the tree so lets remove
it once the last job is consumed. This keeps the tree smaller which is
nicer and more efficient as entities are removed and re-added on every
popped job.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummri
To implement fair scheduling we need a view into the GPU time consumed by
entities. Problem we have is that jobs and entities objects have decoupled
lifetimes, where at the point we have a view into accurate GPU time, we
cannot link back to the entity any longer.
Solve this by adding a light weigh
Fair scheduling policy is built upon the same concepts as the well known
CFS kernel scheduler - entity run queue is sorted by the virtual GPU time
consumed by entities in a way that the entity with least vruntime runs
first.
It is able to avoid total priority starvation, which is one of the
proble
To implement fair scheduling we will need as accurate as possible view
into per entity GPU time utilisation. Because sched fence execution time
are only adjusted for accuracy in the free worker we need to process
completed jobs as soon as possible so the metric is most up to date when
view from the
Move the code dealing with entities entering and exiting run queues to
helpers to logically separate it from jobs entering and exiting entities.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/sched_en
Reduce to one spin_unlock for hopefully a little bit clearer flow in the
function. It may appear that there is a behavioural change with the
drm_sched_start_timeout_unlocked() now not being called if there were
initially no jobs on the pending list, and then some appeared after
unlock, however if t
Currently the job free work item will lock sched->job_list_lock first time
to see if there are any jobs, free a single job, and then lock again to
decide whether to re-queue itself if there are more finished jobs.
Since drm_sched_get_finished_job() already looks at the second job in the
queue we c
To make evaluating different scheduling policies easier (no need for
external benchmarks) and perfectly repeatable, lets add some synthetic
workloads built upon mock scheduler unit test infrastructure.
Focus is on two parallel clients (two threads) submitting different job
patterns and logging the
Move work queue allocation into a helper for a more streamlined function
body.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/sched_main.c | 33 --
1 file changed, 20 insertion
Round-robin being the non-default policy and unclear how much it is used,
we can notice that it can be implemented using the FIFO data structures if
we only invent a fake submit timestamp which is monotonically increasing
inside drm_sched_rq instances.
So instead of remembering which was the last
Extract out two copies of the identical code to function epilogue to make
it smaller and more readable.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/sched_main.c | 48 +++---
1 f
Hi all,
This is another respin of this old work^1 but this version is a total rewrite
and completely changes how the control is done.
This time round the work builds upon the "fair" DRM scheduler work I have posted
recently^2. I am including those patches for completeness and because there were
s
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