In gfx_v12_0_cp_gfx_load_me_microcode_rs64(), gfx_v12_0_pfp_fini() is
incorrectly used to free 'me' field of 'gfx', since gfx_v12_0_pfp_fini()
can only release 'pfp' field of 'gfx'. The release function of 'me' field
should be gfx_v12_0_me_fini().
Fixes: 52cb80c12e8a ("drm/amdgpu: Add gfx v12_0 ip
On Tue, Mar 11, 2025 at 06:20:53PM +0100, José Expósito wrote:
> Hi everyone,
>
> > On Tue, Feb 25, 2025 at 02:51:40PM +0100, Louis Chauvet wrote:
> > >
> > >
> > > Le 25/02/2025 à 12:41, Thomas Zimmermann a écrit :
> > > > Hi
> > > >
> > > > Am 10.02.25 um 15:37 schrieb Louis Chauvet:
> > > >
On Mon, Mar 10, 2025 at 10:12:15PM -0700, Matthew Brost wrote:
> On Mon, Mar 10, 2025 at 10:04:22PM -0700, Matthew Brost wrote:
> > On Mon, Mar 10, 2025 at 09:22:50PM +0300, Dan Carpenter wrote:
> > > On Mon, Mar 10, 2025 at 12:56:46PM -0400, Rodrigo Vivi wrote:
> > > > On Mon, Mar 10, 2025 at 01:4
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Wednesday, March 12, 2025 11:19 AM
> To: Murthy, Arun R ; dri-
> de...@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Cc: Kumar, Naveen1
> Subject: RE: [PATCH v6 2/3] drm/plane: mod
> -Original Message-
> From: dri-devel On Behalf Of
> Arun R Murthy
> Sent: Tuesday, February 25, 2025 1:04 PM
> To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; ville.syrj...@linux.intel.com
> Cc: Murthy, Arun R ; Kumar, Naveen1
> -Original Message-
> From: Murthy, Arun R
> Sent: Wednesday, February 19, 2025 2:47 PM
> To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Murthy,
> Arun R ; Kumar, Naveen1
>
> Subject: [PATCH v6 2/
From: Brost, Matthew
Sent: Monday, March 10, 2025 9:50 PM
To: Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; Gupta, saurabhg; Zuo, Alex;
joonas.lahti...@linux.intel.com; Zhang, Jianxun; Lin, Shuicheng;
dri-devel@lists.freedesktop.org
Subject: Re:
The mediatek display driver fails to probe on mt8173-elm-hana and
mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
configurations.
Enable the following PHY drivers for MediaTek platforms:
- CONFIG_PHY_MTK_HDMI=m for HDMI display
- CONFIG_PHY_MTK_MIPI_DSI=m for DSI display
- CONFI
Hi Piotr,
在 2025-03-10 04:53:50，"Piotr Oniszczuk" 写道：
>
>
>> Wiadomość napisana przez Andy Yan w dniu 7 mar 2025, o
>> godz. 01:48:
>>
>>
>> Hi Piotr,
>> 在 2025-03-06 22:28:08，"Piotr Oniszczuk" 写道：
>>>
>>>
>>
>> All dump information currently appears to be correct, so I'm temporarily
>>
Hi Nícolas,
On 12/03/25 01:15, Nícolas F. R. A. Prado wrote:
On Tue, Mar 11, 2025 at 05:26:37PM +0530, Vignesh Raman wrote:
Hi Krzysztof,
On 11/03/25 12:54, Krzysztof Kozlowski wrote:
On 11/03/2025 07:16, Vignesh Raman wrote:
The mediatek display driver fails to probe on mt8173 and mt8183 in
Hi Daniel,
On 10/03/25 13:53, Daniel Stone wrote:
Hi Vignesh,
On Mon, 17 Feb 2025 at 05:37, Vignesh Raman wrote:
This patch series enables lockdep detection in drm-ci. Any lockdep
failures will be shown as warnings in the pipeline. This series
also enables CONFIG_DEBUG_WW_MUTEX_SLOWPATH for m
From: Jernej Skrabec
Use the new blender register lookup function where required in the layer
commit and update code.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
---
drivers/gpu/drm/sun4i/sun8i_mixer.c
[ My ears have been burning for a couple months regarding this thread
and I have finally had the chance to circle back and read through all
the discussion on PATCH 01/12 and this PATCH 08/12, pardon the latency
while I addressed some CXL backlog ]
Jason Gunthorpe wrote:
> On Mon, Jan 20, 202
On Tue, 25 Feb 2025, at 6:56 AM, Andre Przywara wrote:
Apologies Andre, I came to review your comments on the TCON series and realised
I had missed responding to this comment before sending v8.
>> + - allwinner,sun50i-h616-de33-mixer-0
>>
>>reg:
>> -maxItems: 1
>> +minItems:
在 2025/3/11 19:14, Ryan Roberts 写道:
Hi,
On 11/03/2025 09:34, Huan Yang wrote:
Hi Christoph and Ryan,
Can you help us check vmap_pfn's pfn check is right? Did here mischecked
pfn_valid?
I'm no expert on this piece of code, but I believe pfn_valid() is checking to
see if a pfn is valid *memor
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++--
1 file changed, 2 insertions(+),
Add some basic tests for exercising entity priority handling.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/tests/tests_basic.c | 95 ++-
1 file changed, 94 insertions(+), 1 deletion(
From: Vincent Mailhol
In an upcoming change, GENMASK() and its friends will indirectly
depend on sizeof() which is not available in asm.
Instead of adding further complexity to __GENMASK() to make it work
for both asm and non asm, just split the definition of the two
variants.
Signed-off-by: Vi
The main modification is moving the DP AUX initialization from function
analogix_dp_bind() to analogix_dp_probe(). In order to get the EDID of
eDP panel during probing, it is also needed to advance PM operations to
ensure that eDP controller and phy are prepared for AUX transmission.
Signed-off-by
On Fri, Mar 07, 2025 at 04:14:34AM -0800, H. Peter Anvin wrote:
> On March 7, 2025 4:13:26 AM PST, Ingo Molnar wrote:
> >
> >* Jiri Slaby wrote:
> >
> >> On 07. 03. 25, 12:38, Ingo Molnar wrote:
> >> >
> >> > * Jiri Slaby wrote:
> >> >
> >> > > On 06. 03. 25, 17:25, Kuan-Wei Chiu wrote:
> >> >
The page fault handler should reject write/atomic access to read only
VMAs. Add code to handle this in handle_pagefault after the VMA lookup.
Fixes: 3d420e9fa848 ("drm/xe: Rework GPU page fault handling")
Signed-off-by: Jonathan Cavitt
Suggested-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_gt_p
Add the initial documentation of the Nova project.
The initial project documentation consists out of a brief introduction
of the project, as well as project guidelines both general and nova-core
specific and a task list for nova-core specifically.
The task list is divided into tasks for general R
Consumers of the direct DMA API will have to know which region their
device allocate from in order for them to charge the memory allocation
in the right one.
Let's provide an accessor for that region.
Signed-off-by: Maxime Ripard
---
include/linux/dma-direct.h | 2 ++
kernel/dma/direct.c
Migrate the pagefault struct from xe_gt_pagefault.c to the
xe_gt_pagefault.h header file, along with the associated enum values.
v2: Normalize names for common header (Matt Brost)
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 41 +---
drivers/
Hi Dave, Simona,
Fixes for 6.14.
The following changes since commit 7eb172143d5508b4da468ed59ee857c6e5e01da6:
Linux 6.14-rc5 (2025-03-02 11:48:20 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.14-2025-03-06
for you to fe
Remove support for fb events from backlight subsystem. Provide the
helper backlight_notify_blank_all() instead. Also export the existing
helper backlight_notify_blank() to update a single backlight device.
In fbdev, call either helper to inform the backlight subsystem of
changes to a display's bla
A lot of DisplayPort bridges use HDMI Codec in order to provide audio
support. Present DRM HDMI Audio support has been written with the HDMI
and in particular DRM HDMI Connector framework support, however those
audio helpers can be easily reused for DisplayPort drivers too.
Patches by Hermes Wu th
DisplayPort requires per-segment link training when LTTPR are switched
to non-transparent mode, starting with LTTPR closest to the source.
Only when each segment is trained individually, source can link train
to sink.
Implement per-segment link traning when LTTPR(s) are detected, to
support extern
Take into account LTTPR capabilities when selecting maximum allowed
link rate, number of data lines. Initialize LTTPR before
msm_dp_panel_read_sink_caps, as
a) Link params computation need to take into account LTTPR's caps
b) It appears DPTX shall (re)read DPRX caps after LTTPR detection
Return lt
Recently added Initial LTTPR support in msm/dp has configured LTTPR(s)
to non-transparent mode to enable video output on X1E-based devices
that come with LTTPR on the motherboards. However, video would not work
if additional LTTPR(s) are present between sink and source, which is
the case for USB Ty
Hey,
This introduced a warning on my local builds,
commit 30d5c46444a6aa4c78103fb898250ab5e6e8a97d
Author: Jason-JH Lin
Date: Mon Feb 24 13:12:21 2025 +0800
drm/mediatek: Fix config_updating flag never false when no mbox channel
CC [M] drivers/gpu/drm/mediatek/mtk_dp.o
/raid1/home/air
On 2025-03-10 4:28 pm, Maxime Ripard wrote:
On Mon, Mar 10, 2025 at 02:56:37PM +, Robin Murphy wrote:
On 2025-03-10 12:06 pm, Maxime Ripard wrote:
Consumers of the direct DMA API will have to know which region their
device allocate from in order for them to charge the memory allocation
in t
On Sun, Mar 09, 2025 at 10:13:58AM +0200, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov
>
> Use drm_hdmi_acr_get_n_cts() helper instead of calculating N and CTS
> values in the VC4 driver.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/vc4/vc4_hdmi.c | 10 +++---
> drivers/
Hi,
On 3/6/25 06:42, Balbir Singh wrote:
...
>
> /*
>* The only time there is no vma is when called from
> @@ -728,15 +1000,47 @@ static void __migrate_device_pages(unsigned long
> *src_pfns,
> migrate->pgmap_o
On 3/11/25 6:17 PM, Maxime Ripard wrote:
> On Tue, Mar 11, 2025 at 12:57:38PM +0200, Cristian Ciocaltea wrote:
>> Provide tests to verify that drm_atomic_helper_connector_hdmi_check()
>> helper behaviour when using YUV420 output format is to always set the
>> limited RGB quantization range to 'limi
On 3/11/25 6:12 PM, Maxime Ripard wrote:
> On Tue, Mar 11, 2025 at 12:57:37PM +0200, Cristian Ciocaltea wrote:
>> Introduce a few macros to facilitate setting custom (i.e. non-default)
>> EDID data during connector initialization.
>>
>> This helps reducing boilerplate code while also drops some red
Hi Rob,
On 3/11/25 17:23, Rob Herring wrote:
On Tue, Mar 11, 2025 at 03:13:47PM -0300, Maíra Canal wrote:
V3D 7.1 exposes a new register block, called V3D_SMS. As BCM2712 has a
V3D 7.1 core, add a new register item to its compatible. Similar to the
GCA, which is specific for V3D 3.3, SMS is opt
On March 11, 2025 3:01:30 PM PDT, Yury Norov wrote:
>On Sun, Mar 09, 2025 at 11:48:26PM +0800, Kuan-Wei Chiu wrote:
>> On Fri, Mar 07, 2025 at 12:07:02PM -0800, H. Peter Anvin wrote:
>> > On March 7, 2025 11:53:10 AM PST, David Laight
>> > wrote:
>> > >On Fri, 07 Mar 2025 11:30:35 -0800
>> > >"H
On Sun, Mar 09, 2025 at 11:48:26PM +0800, Kuan-Wei Chiu wrote:
> On Fri, Mar 07, 2025 at 12:07:02PM -0800, H. Peter Anvin wrote:
> > On March 7, 2025 11:53:10 AM PST, David Laight
> > wrote:
> > >On Fri, 07 Mar 2025 11:30:35 -0800
> > >"H. Peter Anvin" wrote:
> > >
> > >> On March 7, 2025 10:49:
Implement a mock scheduler backend and add some basic test to exercise the
core scheduler code paths.
Mock backend (kind of like a very simple mock GPU) can either process jobs
by tests manually advancing the "timeline" job at a time, or alternatively
jobs can be configured with a time duration in
Due to the nature of changes this is probably necessary. Even if these
drawing routines got way more testing than my patch submission scripts.
Signed-off-by: Zsolt Kajtar
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0248c9e
On Wed, 2025-03-05 at 10:10 +0100, Christian König wrote:
> Yeah, it's sad but I probably won't find time for a deeper review
> anytime soon.
>
> So feel free to add my Acked-by as well.
>
> Christian.
Thanks, Christian, I added those acks and pushed the series.
I discussed a bit with Dave and
On Mon, 10 Mar 2025 16:59:18 -0300
Ariel D'Alessandro wrote:
> Both these functions write to MMU_AS_CONTROL register in the same way.
> Define a common _panfrost_mmu_as_control_write function with the shared
> code.
>
> Signed-off-by: Ariel D'Alessandro
> ---
> drivers/gpu/drm/panfrost/panfros
On Thu, 6 Mar 2025 14:45:05 +0100
Danilo Krummrich wrote:
> On Thu, Mar 06, 2025 at 09:56:38PM +0900, FUJITA Tomonori wrote:
>> On Tue, 4 Mar 2025 18:34:52 +0100
>> Danilo Krummrich wrote:
>>
>> > +Delay / Sleep abstractions
>> > +--
>> > +
>> > +Rust abstractions for t
On Tue, Mar 11, 2025 at 09:05:57PM +, Dr. David Alan Gilbert wrote:
> * Mark Brown (broo...@kernel.org) wrote:
> > [6/9] regulator: pcf50633-regulator: Remove
> > commit: 248bc01138b11ff3af38c3b4a39cb8db7aae6eb6
> Thanks!
> AlthoughI'd only tested this as part of the series and assu
* Mark Brown (broo...@kernel.org) wrote:
> On Sun, 09 Mar 2025 19:36:03 +, li...@treblig.org wrote:
> > The pcf50633 was used as part of the OpenMoko devices but
> > the support for its main chip was recently removed in:
> > commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support")
> >
> >
On Mon, Mar 10, 2025 at 03:23:57PM +0800, WangYuli wrote:
> Manifestly, the "ARM devices" menu is appropriate only for the ARM
> architecture.
>
> Inasmuch as every single item in this menu is predicated on
> (ARM || ARM64 || COMPILE_TEST), it is therefore illogical for the
> "ARM devices" menu it
Move drm_of_find_panel_or_bridge() a little later and combine it with
component_add() into a new function rockchip_dp_link_panel(). The function
will serve as done_probing() callback of devm_of_dp_aux_populate_bus(),
aiding to support for obtaining the eDP panel via the DP AUX bus.
If failed to ge
On Thu, Mar 06, 2025 at 10:08:24AM -0500, Anusha Srivatsa wrote:
> On Thu, Mar 6, 2025 at 4:31 AM Maxime Ripard wrote:
>
> > Hi Anusha,
> >
> > On Wed, Mar 05, 2025 at 07:01:41PM -0500, Anusha Srivatsa wrote:
> > > Move away from using deprecated API and use _multi
> > > variants if available. Us
Move the handling of display updates to separate helper functions.
There is code for handling fbdev blank events and fbdev mode changes.
The code currently runs from fbdev event notifiers, which will be
replaced.
Signed-off-by: Thomas Zimmermann
---
drivers/video/backlight/lcd.c | 38 +++
The constants FB_EVENT_MODE_CHANGE and FB_EVENT_BLANK are unused.
Remove them from the header file.
Signed-off-by: Thomas Zimmermann
---
include/linux/fb.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index d45bd220cb8f..2497321e30bb 100644
---
Add a basic test for exercising modifying the entities scheduler list at
runtime.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/tests/tests_basic.c | 69 ++-
1 file changed, 68 insert
Am 10.03.25 um 10:30 schrieb Tvrtko Ursulin:
>
> On 10/03/2025 08:41, Philipp Stanner wrote:
>> On Mon, 2025-03-10 at 08:44 +0100, Christian König wrote:
>>> This reverts commit 44d2f310f008613c1dbe5e234c2cf2be90cbbfab.
>>>
>>> Sorry for the delayed response, I only stumbled over this now while
>>>
On Sun, Mar 09, 2025 at 07:36:09PM +, li...@treblig.org wrote:
> Signed-off-by: Dr. David Alan Gilbert
> ---
> drivers/mfd/pcf50633-core.c| 35 +--
> drivers/regulator/Kconfig | 7 --
> drivers/regulator/Makefile | 1 -
> drivers/regulator/pcf506
Add additional information to each VM so they can report up to the last
50 seen pagefaults. Only failed pagefaults are saved this way, as
successful pagefaults should recover and not need to be reported to
userspace.
Additionally, add a new ioctl - xe_vm_get_faults_ioctl - that allows the
user to
On Tue, Mar 11, 2025 at 03:13:47PM -0300, Maíra Canal wrote:
> V3D 7.1 exposes a new register block, called V3D_SMS. As BCM2712 has a
> V3D 7.1 core, add a new register item to its compatible. Similar to the
> GCA, which is specific for V3D 3.3, SMS is optional and should only be
> added for V3D 7.
On Tue, 11 Mar 2025 01:49:50 +, li...@treblig.org wrote:
> The pcf50633 was used as part of the OpenMoko devices but
> the support for its main chip was recently removed in:
> commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support")
>
> See https://lore.kernel.org/all/Z8z236h4B5A6Ki3D@gall
On Tue, 11 Mar 2025 17:40:05 +0100, Antonin Godard wrote:
> Add POWERTIP PH128800T004-ZZA01 10.1" LCD-TFT LVDS panel compatible
> string.
>
> Signed-off-by: Antonin Godard
> ---
> Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Ac
On Sun, 09 Mar 2025 19:36:03 +, li...@treblig.org wrote:
> The pcf50633 was used as part of the OpenMoko devices but
> the support for its main chip was recently removed in:
> commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support")
>
> See https://lore.kernel.org/all/Z8z236h4B5A6Ki3D@gall
Starting with commit ec3e00b4ee27 ("drm/i915: stop registering if
drm_dev_register() fails"), we return from i915_driver_register()
immediately if drm_dev_register() fails, skipping remaining registration
steps, and continue only with remaining probe steps. However, the
_unregister() counterpart c
* li...@treblig.org (li...@treblig.org) wrote:
> From: "Dr. David Alan Gilbert"
>
> The pcf50633 was used as part of the OpenMoko devices but
> the support for its main chip was recently removed in:
> commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support")
>
> See https://lore.kernel.org/al
Applied. thanks!
On Mon, Mar 10, 2025 at 6:48 AM Dan Carpenter wrote:
>
> These lines are indented one tab more than they should be. Delete
> the stray tabs.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 12 ++--
> 1 file changed, 6 insertions(+), 6
Aspirational unit test mode can be activated via
CONFIG_DRM_SCHED_KUNIT_TEST_ASPIRATIONAL and will test the scheduler not
against the criteria of how it is implemented today, but according to the
future design goals and agreements.
First example of this is the scheduler cleanup flow which currentl
On Mon, Mar 10, 2025 at 02:56:37PM +, Robin Murphy wrote:
> On 2025-03-10 12:06 pm, Maxime Ripard wrote:
> > Consumers of the direct DMA API will have to know which region their
> > device allocate from in order for them to charge the memory allocation
> > in the right one.
>
> This doesn't se
The Allwinner H616 and variants have a new display engine revision
(DE33).
The mixer configuration registers are significantly different to the DE3
and DE2 revisions, being split into separate top and display blocks,
therefore a fallback for the mixer compatible is not provided.
Add a display eng
On Tue, Mar 11, 2025 at 04:55:17PM +0100, Maxime Ripard wrote:
> Hi,
>
> I think the first thing we need to address is that we will need to
> differentiate between HDMI 1.4 devices and HDMI 2.0.
>
> It applies to YUV420, which is HDMI 2.0-only, and I guess your patches
> are good enough if you co
On Tue, Mar 11, 2025 at 12:57:33PM +0200, Cristian Ciocaltea wrote:
> Evaluating the requirement to use a limited RGB quantization range
> involves a verification of the output format, among others, but this is
> currently performed before actually computing the format, hence relying
> on the old c
On Tue, Mar 11, 2025 at 05:26:37PM +0530, Vignesh Raman wrote:
> Hi Krzysztof,
>
> On 11/03/25 12:54, Krzysztof Kozlowski wrote:
> > On 11/03/2025 07:16, Vignesh Raman wrote:
> > > The mediatek display driver fails to probe on mt8173 and mt8183 in
> > > v6.14-rc4, with the following errors:
> >
>
On Tue, Mar 11, 2025 at 05:40:06PM +0100, Antonin Godard wrote:
> Add support for the POWERTIP PH128800T004-ZZA01 10.1" (1280x800)
> LCD-TFT panel. Its panel description is very much like the POWERTIP
> PH128800T006-ZHC01 configured below this one, only its timings are
> different.
>
> Signed-off-
On Sun, Mar 09, 2025 at 09:33:55AM +0530, Tejas Vipin wrote:
> Changes the novatek-nt36523 panel to use multi style functions for
> improved error handling.
>
> Signed-off-by: Tejas Vipin
> ---
> Changes in v3:
> - Remove mipi_dsi_dual_msleep
> - Change mipi_dsi_dual_dcs_write_seq_multi t
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.ker
On Sun, Mar 09, 2025 at 10:13:56AM +0200, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov
>
> HDMI standard defines recommended N and CTS values for Audio Clock
> Regeneration. Currently each driver implements those, frequently in
> somewhat unique way. Provide a generic helper for getting those
Il 10/03/25 20:59, Ariel D'Alessandro ha scritto:
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del
From: Dmitry Baryshkov
Switch drm_dp_aux_dev.c to use new set of DPCD read / write helpers.
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_aux_dev.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/displ
Hi all,
Following the previous RFC [0], this is the first iteration on Panfrost
support for AARCH64_4K page table format.
Currently, Panfrost only supports MMU configuration in LEGACY mode, as
named by Bifrost. This is a (modified) version of LPAE "Large Physical
Address Extension", which in Linu
Hi Yury,
On Fri, Mar 07, 2025 at 10:55:13AM -0500, Yury Norov wrote:
> On Fri, Mar 07, 2025 at 07:57:48AM +0100, Jiri Slaby wrote:
> > On 06. 03. 25, 17:25, Kuan-Wei Chiu wrote:
> > > Several parts of the kernel contain redundant implementations of parity
> > > calculations for 16/32/64-bit values
Hi Dave and Sima,
Here goes our xe fixes for this round, with
many fixes around userptr.
Thanks,
Rodrigo.
drm-xe-fixes-2025-03-06:
- Remove double page flip on initial plane (Maarten)
- Properly setup userptr pfn_flags_mask (Auld)
- Fix GT "for each engine" workarounds (Tvrtko)
- Fix userptr rac
On 03/11, Alex Hung wrote:
> This macro guard "__cplusplus" is unnecessary and should not be there.
>
> Signed-off-by: Alex Hung
> ---
> drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h
> b/driv
Add support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm/ms
v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe
rectangle to be programmed separately in blend stage. Implement support
for this along with a new CTL_LAYER_ACTIVE register and setting the
blend stage in layer mixer code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzyszt
v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
selective activation of pipes, which replaces earlier
dpu_hw_ctl_setup_blendstage() code path for newer devices.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex
2. Add Dmitry's t
Add DPU version v12.0 support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2:
1. Add CDM
---
.../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 496 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/driver
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8
1 file
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out,
setup_border_color and so one for this.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex, use spaces for define indentation
2. _dpu_crtc_setup_blend_cfg
Add support for DSI on Qualcomm SM8750 SoC with notable difference:
DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
parents before DSI PHY is configured and the PLLs are prepared with
initial rate is set. Therefore assigned-clock-parents are not working
here and driver is re
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an
incompatible hardware interface change:
ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
offsets were just switched. Currently these registers are not used in
the driver, so the easiest is to document both
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Resetting mixers should also include resetting active fetch pipes.
Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw
blocks")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
dr
Before blend setup, all existing blend stages are cleared, so shall be
active fetch pipes.
Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in
ctl path")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from pre
Resetting entire CTL path should also include resetting active fetch
pipes.
Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and
newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to
set_active_fetch_pipes() to better match the purpose.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2
Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.
Reviewed-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. Properly described interconnects
2. Use only one compatible and contains for
Add DPU for Qualcomm SM8750 SoC which has several differences, new
blocks and changes in registers, making it incompatible with SM8650.
Acked-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1
Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
fully compatible with earlier SM8650 variant - both are of version
v1.5.1 of the IP block. Datasheet also mentions that both support 4x
MST for DPTX0 and 2x MST for DPTX1.
Acked-by: Rob Herring (Arm)
Reviewed-by: Dmitry Barysh
Add DSI controller for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
It does not allow the display clock controller clocks like "byte" and
"pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not
configured (not prepared, rate not set). Therefore
ass
Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
Acked-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentatio
Hi,
Dependency / Rabased on top of
==
https://lore.kernel.org/all/20241214-dpu-drop-features-v1-0-988f0662c...@linaro.org/
Merging
===
DSI pieces here might not be ready - I got modetest writeback working,
but DSI panel on MTP8750 still shows darkness. Therefore w
In the ttm_bo_unreserve_bulk() test function, resv is allocated
using kunit_kzalloc(), but the subsequent assertion mistakenly
verifies the ttm_dev pointer instead of checking the resv pointer.
This mistake means that if allocation for resv fails, the error will
go undetected, resv will be NULL
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