On 20-02-2025 21:56, Dmitry Baryshkov wrote:
On Tue, Feb 18, 2025 at 11:13:39AM +0530, Murthy, Arun R wrote:
On 17-02-2025 15:38, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are no
On 20-02-2025 21:20, Pekka Paalanen wrote:
On Wed, 19 Feb 2025 09:28:51 +0530
"Murthy, Arun R" wrote:
On 18-02-2025 21:48, Pekka Paalanen wrote:
On Tue, 18 Feb 2025 11:13:39 +0530
"Murthy, Arun R" wrote:
On 17-02-2025 15:38, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be
On 17-02-2025 17:57, Pekka Paalanen wrote:
On Mon, 17 Feb 2025 12:08:08 +0200
Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both are
On 19-02-2025 19:01, Simona Vetter wrote:
On Mon, Feb 17, 2025 at 06:26:17PM +0100, Simona Vetter wrote:
On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header
On Fri, Feb 28, 2025 at 09:08:15PM +0200, Raag Jadav wrote:
> On Fri, Feb 28, 2025 at 08:52:51PM +0200, Andy Shevchenko wrote:
> > On Fri, Feb 28, 2025 at 08:45:26PM +0200, Raag Jadav wrote:
> > > On Fri, Feb 28, 2025 at 08:42:10PM +0200, Andy Shevchenko wrote:
> > > > On Fri, Feb 28, 2025 at 08:41
On Sat, 22 Feb 2025, Antheas Kapenekakis wrote:
> The X1 devices come with a pen-capable touchscreen, in which the HID
> descriptor reports there is always a battery at 100% charge. Quirk it
> to not report the battery status.
>
> Signed-off-by: Antheas Kapenekakis
Let me provide
Acked
On Mon, Mar 03, 2025 at 01:01:40AM +0200, Dmitry Baryshkov wrote:
> On Sun, Mar 02, 2025 at 09:56:00PM +0100, Markus Elfring wrote:
> > From: Markus Elfring
> > Date: Tue, 11 Apr 2023 18:24:24 +0200
> >
> > The address of a data structure member was determined before
> > a corresponding null poin
Hi Heiko,
At 2025-03-03 02:57:50, "Heiko Stübner" wrote:
>Hi Andy,
>
>Am Dienstag, 18. Februar 2025, 12:27:34 MEZ schrieb Andy Yan:
>> From: Andy Yan
>>
>> In the upcoming VOP of rk3576, a Window cannot attach to all Video Ports,
>> so make sure all VP find it's suitable primary plane, then re
On Mon, Mar 03, 2025 at 01:02:44PM +0800, Yongbang Shi wrote:
>
> > On Sat, 1 Mar 2025 at 11:54, Yongbang Shi wrote:
> > >
> > > > On Sat, Mar 01, 2025 at 04:45:40PM +0800, Yongbang Shi wrote:
> > > > > > On Thu, Feb 27, 2025 at 09:46:10PM +0800, Yongbang Shi wrote:
> > > > > > > > On Tue, Feb 2
On Sat, 1 Mar 2025 at 11:54, Yongbang Shi wrote:
On Sat, Mar 01, 2025 at 04:45:40PM +0800, Yongbang Shi wrote:
On Thu, Feb 27, 2025 at 09:46:10PM +0800, Yongbang Shi wrote:
On Tue, Feb 25, 2025 at 09:57:17PM +0800, Yongbang Shi wrote:
On Mon, 24 Feb 2025 at 16:03, Yongbang Shi wrote:
O
From: Andy Yan
VOP2 on rk3576:
Three video ports:
VP0 Max 4096x2160
VP1 Max 2560x1600
VP2 Max 1920x1080
2 4K Cluster windows with AFBC/RFBC, line RGB and YUV
4 Esmart windows with line RGB/YUV support:
Esmart0/1: 4K
Esmart2/3: 2k, or worked together as a single 4K plane at shared
line buffer mod
From: Andy Yan
The clock polarity of RGB signal output is controlled by GRF, this
property is already being used in the current device tree, but
forgot to describe it as a required property in the binding file.
Signed-off-by: Andy Yan
Acked-by: Krzysztof Kozlowski
---
(no changes since v13)
From: Andy Yan
The Cluster windows of upcoming VOP on rk3576 also support
linear YUV support, we need to set uv swap bit for it.
As the VOP2_WIN_UV_SWA register defined on rk3568/rk3588 is
0x, so this register will not be touched on these
two platforms.
Signed-off-by: Andy Yan
Tested-b
From: Andy Yan
Here is the v16
Patches that have already been merged in drm-misc-next are dropped.
I test it with a 1080P/4K HDMI output with modetest and weston
output.
If there are some one want to have a try, I have a tree based on
Linux 6.14-rc1 here[0]
[0]https://github.com/andyshrk/linux
From: Andy Yan
In the upcoming VOP of rk3576, a window cannot attach to all Video
Ports, we introduce a possible_vp_mask for every window to indicate
which Video Ports this window can attach to.
Signed-off-by: Andy Yan
Tested-by: Michael Riesch # on RK3568
Tested-by: Detlev Casanova
---
(no
From: Andy Yan
As more SoCs variants are introduced, each SoC brings its own
unique set of constraints, describe this constraints SoC by
SoC will make things easier.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
(no changes since v14)
Changes in v14:
- Set maxItems constraint
From: Andy Yan
Add vop found on rk3576, the main difference between rk3576 and the
previous vop is that each VP has its own interrupt line.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
(no changes since v13)
Changes in v13:
- Use maxItems constraint for clocks in allOf block
From: Andy Yan
In the upcoming VOP of rk3576, a Window cannot attach to all Video Ports,
so make sure all VP find it's suitable primary plane, then register the
remain windows as overlay plane will make code easier.
Signed-off-by: Andy Yan
Tested-by: Michael Riesch # on RK3568
Tested-by: Detle
On Sun, Mar 02, 2025 at 07:09:54PM +, David Laight wrote:
> On Mon, 3 Mar 2025 01:29:19 +0800
> Kuan-Wei Chiu wrote:
>
> > Hi Yury,
> >
> > On Sun, Mar 02, 2025 at 11:02:12AM -0500, Yury Norov wrote:
> > > On Sun, Mar 02, 2025 at 04:20:02PM +0800, Kuan-Wei Chiu wrote:
> > > > Hi Yury,
> >
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
between commits:
e7ea88207cef ("drm/amdgpu/gfx: only call mes for enforce isolation if
supported")
748a1f51bb74 ("drm/amdgpu/mes: keep enforce isolation up to date")
from Linus' t
On Sun, Mar 02, 2025 at 09:56:00PM +0100, Markus Elfring wrote:
> From: Markus Elfring
> Date: Tue, 11 Apr 2023 18:24:24 +0200
>
> The address of a data structure member was determined before
> a corresponding null pointer check in the implementation of
> the functions “dpu_hw_pp_enable_te” and “
Tested this on a RG35XX-H (H700),
launching glmark2-es2-drm completely hangs the board.
No kernel oops or error messages.
Philippe
On 21/02/2025 01:57, Andre Przywara wrote:
The Allwinner H616/H618/H313/H700 SoCs contain a Mali G32 MP2 GPU. This
IP is from the Bifrost family and is already su
From: Christian Göttsche
capable() calls refer to enabled LSMs whether to permit or deny the
request. This is relevant in connection with SELinux, where a
capability check results in a policy decision and by default a denial
message on insufficient permission is issued.
It can lead to three unde
From: Markus Elfring
Date: Fri, 28 Feb 2025 16:37:00 +0100
Replace nested max() calls by single max3() call in this
function implementation.
This issue was transformed by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
1 file changed, 1
From: Markus Elfring
Date: Tue, 11 Apr 2023 18:24:24 +0200
The address of a data structure member was determined before
a corresponding null pointer check in the implementation of
the functions “dpu_hw_pp_enable_te” and “dpu_hw_pp_get_vsync_info”.
Thus avoid the risk for undefined behaviour by r
On Sun, Mar 2, 2025 at 7:31 PM Jarkko Sakkinen wrote:
>
> Ah, ok, I guessed that you might have some backing idea on what you put
> :-) Thanks for the explanation.
You're welcome!
Cheers,
Miguel
On Mon, 3 Mar 2025 01:29:19 +0800
Kuan-Wei Chiu wrote:
> Hi Yury,
>
> On Sun, Mar 02, 2025 at 11:02:12AM -0500, Yury Norov wrote:
> > On Sun, Mar 02, 2025 at 04:20:02PM +0800, Kuan-Wei Chiu wrote:
> > > Hi Yury,
> > >
> > > On Sat, Mar 01, 2025 at 10:10:20PM -0500, Yury Norov wrote:
> > > >
Hi Andy,
Am Dienstag, 18. Februar 2025, 12:28:58 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> VOP2 on rk3576:
> Three video ports:
> VP0 Max 4096x2160
> VP1 Max 2560x1600
> VP2 Max 1920x1080
>
> 2 4K Cluster windows with AFBC/RFBC, line RGB and YUV
> 4 Esmart windows with line RGB/YUV support:
>
Hi Andy,
Am Dienstag, 18. Februar 2025, 12:27:34 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> In the upcoming VOP of rk3576, a Window cannot attach to all Video Ports,
> so make sure all VP find it's suitable primary plane, then register the
> remain windows as overlay plane will make code easier.
On Tue, 18 Feb 2025 19:27:27 +0800, Andy Yan wrote:
> PATCH 1~9 are preparations for rk3576 support
> PATCH 10~13 are real support for rk376
>
> I test it with a 1080P/4K HDMI output with modetest and weston
> output.
>
> If there are some one want to have a try, I have a tree based on
> Linux
On Sun, Mar 02, 2025 at 06:45:13PM +0100, Miguel Ojeda wrote:
> On Sun, Mar 2, 2025 at 5:50 PM Jarkko Sakkinen wrote:
> >
> > (cosmetic) Nit:
> >
> > I think you could just:
> >
> > Cc: sta...@vger.kernel.org # v6.12+
>
> Thanks Jarkko -- I did something similar in the past, but sometimes
> patch
From: Markus Elfring
Date: Thu, 13 Apr 2023 21:35:36 +0200
The address of a data structure member was determined before
a corresponding null pointer check in the implementation of
the function “au1100fb_setmode”.
Thus avoid the risk for undefined behaviour by moving the assignment
for the variab
On Sun, Mar 2, 2025 at 5:50 PM Jarkko Sakkinen wrote:
>
> (cosmetic) Nit:
>
> I think you could just:
>
> Cc: sta...@vger.kernel.org # v6.12+
Thanks Jarkko -- I did something similar in the past, but sometimes
patches got backported too much because they could be applied.
Normally they don't hur
Hi Yury,
On Sun, Mar 02, 2025 at 11:02:12AM -0500, Yury Norov wrote:
> On Sun, Mar 02, 2025 at 04:20:02PM +0800, Kuan-Wei Chiu wrote:
> > Hi Yury,
> >
> > On Sat, Mar 01, 2025 at 10:10:20PM -0500, Yury Norov wrote:
> > > On Sat, Mar 01, 2025 at 10:23:52PM +0800, Kuan-Wei Chiu wrote:
> > > > Add g
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月18日 週二 下午5:04寫道：
>
> Add compatible for Display Stream Compression (DSC) IP found in
> the display controller of the MT8188 SoC.
>
> This IP is fully compatible with the one found on MT8195.
Applied to mediatek-drm-next [1], thanks.
[1]
https://w
On Sun, Mar 02, 2025 at 06:34:22PM +0800, Andy Yan wrote:
>
>
> Hi Dmitry，
>Thank you for your review。
>Please also review my inline reply.
>
> 在 2025-03-02 02:14:19，"Dmitry Baryshkov" 写道：
> >On Sun, Feb 23, 2025 at 07:30:25PM +0800, Andy Yan wrote:
> >> From: Andy Yan
> >>
> >>
On Sat, Mar 1, 2025, at 23:01, Alyssa Rosenzweig wrote:
> Apple GPUs support various non-linear image layouts. Add modifiers for
> these layouts. Mesa requires these modifiers to share non-linear buffers
> across processes, but no other userspace or kernel support is
> required/expected.
>
> These
On Sun, Mar 02, 2025 at 04:20:02PM +0800, Kuan-Wei Chiu wrote:
> Hi Yury,
>
> On Sat, Mar 01, 2025 at 10:10:20PM -0500, Yury Norov wrote:
> > On Sat, Mar 01, 2025 at 10:23:52PM +0800, Kuan-Wei Chiu wrote:
> > > Add generic C implementations of __paritysi2(), __paritydi2(), and
> > > __parityti2()
+CC: Linus
On Wed, Jan 22, 2025 at 11:41 PM Jani Nikula wrote:
>
> Ensure drm headers build, are self-contained, have header guards, and
> have no kernel-doc warnings, when CONFIG_DRM_HEADER_TEST=y.
>
> The mechanism follows similar patters used in i915, xe, and usr/include.
>
> To cover include/
On Thu, Feb 27, 2025 at 09:57:41PM +, David Laight wrote:
> > It's still unclear to me that this parity thing is used in hot paths.
> > If that holds, it's unclear that your hand-made version is better than
> > what's generated by GCC.
>
> I wasn't seriously considering doing that optimisation
On Mon, Mar 11, 2024 at 9:33 PM Jani Nikula wrote:
>
> On Fri, 08 Mar 2024, Jani Nikula wrote:
> > Ensure drm headers build, are self-contained, have header guards, and
> > have no kernel-doc warnings, when CONFIG_DRM_HEADER_TEST=y.
> >
> > The mechanism follows similar patters used in i915, xe,
Hi, Anusha:
Anusha Srivatsa 於 2025年2月14日 週五 上午8:20寫道：
>
> Replace platform_get_resource + devm_ioremap_resource
> with just devm_platform_ioremap_resource()
>
> Used Coccinelle to do this change. SmPl patch:
> @rule_1@
> identifier res;
> expression ioremap_res;
> identifier pdev;
> @@
> -struct
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/intel_nvm.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
di
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 +++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---
drivers/gpu/drm/xe/
Enable access to internal non-volatile memory on DGFX
with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c |
Enable access to internal non-volatile memory on
DGFX devices via a child device.
The nvm child device is exposed via auxiliary bus.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/
Enable runtime PM in mtd driver to notify graphics driver that
whole card should be kept awake while nvm operations are
performed through this driver.
CC: Lucas De Marchi
Acked-by: Karthik Poosa
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd_intel_dg.c |
GSC NVM controller HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd_intel_dg.c | 35 ++
1 file changed, 35 insertions(
Register the on-die nvm device with the mtd subsystem.
Refcount nvm object on _get and _put mtd callbacks.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Acked-by: Miquel Raynal
Co-de
Implement read(), erase() and write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Co-developed-by: Vitaly Lubart
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mt
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/mtd/
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS| 7 ++
dr
Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.
This streamlines device tree and allows to anchor
runtime power management on master device in all cases.
Signed-off-by: Alexander Usyskin
---
drivers/mtd/mtdcore.c | 141 +--
Add driver for access to Intel discrete graphics card
internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
and "spi: add driver for Intel d
On Wed, Feb 26, 2025 at 12:28 PM Thomas Zimmermann
wrote:
> Add drm_gem_is_imported() that tests if a GEM object's buffer has
> been imported. Update the GEM code accordingly.
>
> GEM code usually tests for imports if import_attach has been set
> in struct drm_gem_object. But attaching a dma-buf
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> Add support for the DPI block found in the MT8195 and MT8188 SoCs.
> Inside of the SoC, this block is directly connected to the HDMI IP.
After fix conflicts, applied to mediatek-drm-next [1], thanks.
[1]
https://web.git.kern
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for MT8195's HDMI reserved
> DPI, add calls to clk_prepare_enable() / clk_disable_unprepare()
> for the TVD clock: in this particular case, the aforementioned
> clock is not (and cannot be) par
Chun-Kuang Hu 於 2025年3月2日 週日 下午7:29寫道：
>
> Hi, Angelo:
>
> AngeloGioacchino Del Regno 於
> 2025年2月17日 週一 下午11:49寫道：
> >
> > On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
> > (afifo) supports outputting either one or two pixels per round
> > regardless of the input being 1T1P or 1
Hello Heiko，
At your earliest convenience, could you kindly have a look whether this
patch series is currently eligible for merge ?
I still hope it can land Linux 6.15 merge window. Please let me know if i
need do some fix or rebase"
At 2025-02-18 19:27:27, "Andy Yan" wrote:
>From:
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
> (afifo) supports outputting either one or two pixels per round
> regardless of the input being 1T1P or 1T2P.
>
> Add a `output_1pixel` member to struct mtk_dpi_c
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> On some SoCs, like MT8195 and MT8188, the DPI instance that is
> reserved to the HDMI Transmitter uses a different clock topology.
>
> In this case, the DPI is clocked by the HDMI IP, and this outputs
> its clock to the MM inpu
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for MT8195's HDMI reserved DPI
> instance, move the input_2p_en bit for DP_INTF to platform data.
>
> While at it, remove the input_2pixel member from platform data as
> having this bit implies
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for the DPI IP found in MT8195
> and in MT8188 used for HDMI, move the code flow for calculation
> and setting of the DPI pixel clock to a separate function called
> mtk_dpi_set_pixel_clk().
>
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for newer DPI instances which
> do support direct-pin but do not have any H_FRE_CON register,
> like the one found in MT8195 and MT8188, add a branch to check
> if the reg_h_fre_con variable wa
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> Setting the TVD PLL clock requires to multiply the target pixel
> clock by a specific constant factor to achieve the target PLL
> frequency, and this is done to reduce jitter to acceptable levels.
>
> On all MediaTek SoCs, the
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> Setting the TVD PLL clock requires to multiply the target pixel
> clock by a specific constant factor to achieve the target PLL
> frequency, and this is done to reduce jitter to acceptable levels.
>
> On all MediaTek SoCs, the
Hi Dmitry,
At 2025-03-02 02:19:24, "Dmitry Baryshkov" wrote:
>On Sun, Feb 23, 2025 at 07:30:26PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> Add driver extension for Synopsys DesignWare DPTX IP used
>> on Rockchip RK3588 SoC.
>>
>> Signed-off-by: Andy Yan
>> ---
>>
>> drivers/gpu/drm/ro
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> This IP includes a Pattern Generator which is useful for debugging
> and testing purposes: add the relevant register and bits to the
> mtk_dpi_regs.h header, and implement support for it in mtk_dpi.
>
> Adding this required to
Hi Doug,
On 2025/2/25 9:41, Doug Anderson wrote:
Hi,
On Mon, Feb 24, 2025 at 12:14 AM Damon Ding wrote:
The main modification is moving the DP AUX initialization from function
analogix_dp_bind() to analogix_dp_probe(). In order to get the EDID of
eDP panel during probing, it is also needed t
Hi Dmitry，
Thank you for your review。
Please also review my inline reply.
在 2025-03-02 02:14:19，"Dmitry Baryshkov" 写道：
>On Sun, Feb 23, 2025 at 07:30:25PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> The DW DP TX Controller is compliant with the DisplayPort Specification
>> Vers
Hi, Angelo:
AngeloGioacchino Del Regno 於
2025年2月17日 週一 下午11:49寫道：
>
> Add compatibles for the Digital Parallel Interface (DPI) block
> found in the MT8195 and MT8188 SoCs: inside of the chip, this one
> is directly connected to the HDMI block.
Applied to mediatek-drm-next [1], thanks.
[1]
http
Hello drm maintainers,
Could you please Ack this patch to get this merged through drm-intel-next..
Thanks
Vinod
On Fri, 2025-02-28 at 11:37 +0200, Vinod Govindapillai wrote:
> Add a const qualifier for the "state" parameter as well as we could
> use this helper to get the combined damage in case
With the commit f37952339cc2 ("drm/bridge: analogix_dp: handle clock via
runtime PM"), the PM operations can help enable/disable the clock. The
err_disable_clk label and clk_disable_unprepare() operations are no
longer necessary because the analogix_dp_resume() will not be called
during probing.
F
Hi Yury,
On Sat, Mar 01, 2025 at 10:10:20PM -0500, Yury Norov wrote:
> On Sat, Mar 01, 2025 at 10:23:52PM +0800, Kuan-Wei Chiu wrote:
> > Add generic C implementations of __paritysi2(), __paritydi2(), and
> > __parityti2() as fallback functions in lib/parity.c. These functions
> > compute the pari
74 matches
Mail list logo
