The Anbernic RG28XX is a handheld gaming device with a 2.8 inch 480x640
display. Add support for the display panel.
This panel is driven by a variant of ST7701 driver IC internally,
confirmed by dumping and analyzing its BSP initialization sequence
by using a logic analyzer. It is very similar to
The RG28XX panel is a display panel of the Anbernic RG28XX, a handheld
gaming device from Anbernic. It is 2.8 inches in size (diagonally) with
a resolution of 480x640.
This panel is driven by a variant of the ST7701 driver IC internally,
confirmed by dumping and analyzing its BSP initialization se
The ST7701 supports not only MIPI DSI, but also SPI as an interface
for configuration. To support a panel connected via SPI with an RGB
parallel interface, add support for SPI using MIPI DBI helpers.
Signed-off-by: Hironori KIKUCHI
Reviewed-by: Neil Armstrong
---
drivers/gpu/drm/panel/Kconfig
Split into a DSI-specific part and a DRM-specific part.
Additionally, use devm_add_action_or_reset() to simplify the flow,
and disable and unprepare the panel on cleanup.
Signed-off-by: Hironori KIKUCHI
Reviewed-by: Neil Armstrong
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 72
Rename DSI_CMD* macros to ST7701_CMD*, and ST7701_DSI macro to
ST7701_WRITE, because they do not belong to DSI.
Signed-off-by: Hironori KIKUCHI
Reviewed-by: Neil Armstrong
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 736 +-
1 file changed, 368
Add support for the display panel of the Anbernic RG28XX, a handheld
gaming device from Anbernic. "RG28XX" is the actual name of the device.
This panel is driven by a variant of the ST7701 driver IC internally,
and is connected via an RGB parallel interface for image transmission and
an SPI interf
Aside from the MDSS<->MEM interconnect, display devices have separate
interconnect for register access. Add this interconnect to the display
node.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/
Enable CONFIG_REGULATOR_QCOM_REFGEN and build it as a module. It is an
internal supply used by the DSI on SM8350-based platforms (e.g. on the
SM8350 HDK device).
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/config
On SM8350 platform the DSI internally is using the refgen regulator. Add
corresponding device node and link it as a supply to the DSI node.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qco
The msm-5.x kernels have additional display RSC and separate display BCM
voter. Since upstream kernel doesn't yet provide display RSC, we end up
duplicating several nodes, which can result in incorrect votes being
cast. Drop *_DISP nodes.
Fixes: fafc114a468e ("interconnect: qcom: Add SM8450 interc
Enable the generic icc sync_state callback to ensure interconnect votes
are actually taken into account, instead of being forced to the maximum
value.
Fixes: b95b668eaaa2 ("interconnect: qcom: icc-rpmh: Add BCMs to commit list in
pre_aggregate")
Signed-off-by: Dmitry Baryshkov
---
drivers/inter
Vendor msm-5.x kernels declared duplicate indices for some of display
nodes to be used by separate display RSC and BCM voters. As it is not
clear how this separate BCM should be modelled upstream and the device
trees do not use these indices, drop them for now.
Signed-off-by: Dmitry Baryshkov
---
Vendor msm-5.x kernels declared duplicate indices for some of display
nodes to be used by separate display RSC and BCM voters. As it is not
clear how this separate BCM should be modelled upstream and the device
trees do not use these indices, drop them for now.
Signed-off-by: Dmitry Baryshkov
---
The msm-5.x kernels have additional display RSC and separate display BCM
voter. Since upstream kernel doesn't yet provide display RSC, we end up
duplicating several nodes, which can result in incorrect votes being
cast. Drop *_DISP nodes.
Fixes: d26a56674497 ("interconnect: qcom: Add SM8350 interc
According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.
Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and
SM8450")
Signed-off-by: Dmitry Baryshkov
---
drivers/
A set of fixes that target stability of the SM8350 platform.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (11):
clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks
clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL
drm/msm/dsi: correct prog
According to msm-5.10 the lucid 5lpe PLLs have require slightly
different configuration that trion / lucid PLLs, it doesn't set
PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the
display clock controller on Qualcomm SM8350 platform.
Fixes: 205737fe3345 ("clk: qcom: add support fo
Add CLK_SET_RATE_PARENT for several branch clocks. Such clocks don't
have a way to change the rate, so set the parent rate instead.
Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150
and SM8250")
Cc: sta...@vger.kernel.org
Signed-off-by: Dmitry Baryshkov
---
drivers
Hi Cristian,
Will you find some time and motivation to add CEC support to Quad-Pixel (QP) TX
controller ?
Probably you recall - I added initial CEC support to yours v1 series and i’m
stuck with timing issue (cec pulses are 3x too long).
For me it looks like clock issue.
I’m out of ideas how to
Adhere to Linux kernel coding style
Reported by checkpatch:
CHECK: mutex definition without comment
Proof for comment:
1. The mutex is used to protect access to the 'running' list
(line 1798 tsi148_dma_list_exec function)
mutex_lock(&ctrlrl->mtx);
if (!list_empty(&ctrlr->running
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