[PATCH 03/11] drm/msm/dsi: correct programming sequence for SM8350 / SM8450

[Dmitry Baryshkov]

According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.

Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and 
SM8450")
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b59137ca674..031446c87dae 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -135,7 +135,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, 
struct dsi_pll_config
                        config->pll_clock_inverters = 0x00;
                else
                        config->pll_clock_inverters = 0x40;
-       } else {
+       } else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
                if (pll_freq <= 1000000000ULL)
                        config->pll_clock_inverters = 0xa0;
                else if (pll_freq <= 2500000000ULL)
@@ -144,6 +144,16 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, 
struct dsi_pll_config
                        config->pll_clock_inverters = 0x00;
                else
                        config->pll_clock_inverters = 0x40;
+       } else {
+               /* 4.2, 4.3 */
+               if (pll_freq <= 1000000000ULL)
+                       config->pll_clock_inverters = 0xa0;
+               else if (pll_freq <= 2500000000ULL)
+                       config->pll_clock_inverters = 0x20;
+               else if (pll_freq <= 3500000000ULL)
+                       config->pll_clock_inverters = 0x00;
+               else
+                       config->pll_clock_inverters = 0x40;
        }
 
        config->decimal_div_start = dec;

-- 
2.39.2