The sta_himax83102 panel sometimes shows abnormally flickering
horizontal lines. The front gate output will precharge the X point of
the next pole circuit before TP(TouchPanel Enable) term starts, and wait
until the end of the TP term to resume the CLK. For this reason, the X
point must be maintain
At present, we have found that there may be a problem of blurred
screen during fast sleep/resume. The direct cause of the blurred
screen is that the IC does not receive 0x28/0x10. Because of the
particularity of the IC, before the panel enters sleep hid must
stop scanning, i2c_hid_core_suspend befo
From: Linus Walleij
The Starry ILI9882t-based panel should never have been part of the boe
tv101wum driver, it is clearly based on the Ilitek ILI9882t display
controller and if you look at the custom command sequences for the
panel these clearly contain the signature Ilitek page switch (0xff)
com
Linus series proposed to break out ili9882t as separate driver,
but he didn't have time for that extensive rework of the driver.
As discussed by Linus and Doug [1], keep macro using the "struct panel_init_cmd"
until we get some resolution about the binary size issue.
[1]:
https://lore.kernel.org
In ch7006_encoder_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/i2c/ch7006_drv.c | 6 --
1 file changed, 4 inserti
In nv17_tv_get_ld_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 2 ++
1 file changed, 2 insert
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/panel/panel-tpo-tpg110.c | 2 ++
1 file changed, 2 insert
In versatile_panel_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/panel/panel-arm-versatile.c | 2 ++
1 file changed, 2
Hi Ma,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v6.6-rc4 next-20231006]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
include/uapi/drm/nouveau_drm.h:49: warning: Cannot understand *
@NOUVEAU_GETPARAM_EXEC_PUSH_MAX
on line 49 - I thought it was a doc line
Fixes: d59e75eef52d ("drm/nouveau: exec: report max pushs through getparam")
Signed-off-by: Randy Dunlap
Cc: Dave Airlie
Cc: Danilo Krummrich
Cc: Karol Her
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_
On Fri, Oct 06, 2023 at 03:14:04PM +, Matthew Brost wrote:
> On Fri, Oct 06, 2023 at 08:59:15AM +0100, Tvrtko Ursulin wrote:
> >
> > On 05/10/2023 05:13, Luben Tuikov wrote:
> > > On 2023-10-04 23:33, Matthew Brost wrote:
> > > > On Tue, Sep 26, 2023 at 11:32:10PM -0400, Luben Tuikov wrote:
>
Quoting Dmitry Baryshkov (2023-09-03 15:24:32)
> Read the downstream port info and set the subconnector type accordingly.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
The is_connected flag is set to true after DP mainlink successfully
finishes link training to enter into ST_MAINLINK_READY state rather
than being set after the DP dongle is connected. Rename the
is_connected flag with link_ready flag to match the state of DP
driver's state machine.
Changes in v5:
Currently the dp_display_request_irq() is executed at
msm_dp_modeset_init() which ties irq registering to the DPU device's
life cycle, while depending on resources that are released as the DP
device is torn down. Move register DP driver irq handler to
dp_display_probe() to have dp_display_irq_handl
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
bridge.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver
during generic_edp_panel_probe() due to AUX DPCD read failed at
edp panel driver. Incorporate PM runtime framework into DP driver so
that host controller's power
Currently eDP population is done at msm_dp_modeset_init() which happen
at binding time. Move eDP population to be done at display probe time
so that probe deferral cases can be handled effectively.
wait_for_hpd_asserted callback is added during drm_dp_aux_init()
to ensure eDP's HPD is up before pro
Original both parser->parse() and dp_power_client_init() are done at
dp_display_bind() since eDP population is done at binding time.
In the preparation of having eDP population done at probe() time,
move both function from dp_display_bind() to dp_display_probe().
Changes in v6:
-- move dp_power_cl
EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
DP host controller. Since external DP host controller initialization had
been incorporated into pm_runtime_resume(), this flag became obsolete.
msm_dp_irq_postinstall() which triggers EV_HPD_INIT_SETUP event is
obsoleted accor
The purpose of this patch series is to incorporate pm runtime framework
into MSM eDP/DP driver so that eDP panel can be detected by DRM eDP panel
driver during system probe time. During incorporating procedure, original
customized pm realted fucntions, such as dp_pm_prepare(), dp_pm_suspend(),
dp_p
On 10/3/2023 13:58, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 03:25:08PM -0700, john.c.harri...@intel.com
wrote:
From: John Harrison
The GuC has been extended to support a much more friendly engine
busyness interface. So partition the old interface into a 'busy_v1'
space and add 'bu
On Wed, Aug 30, 2023 at 07:15:27PM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> The PCI code and ID assignment specification defined four types of
> display controllers for the display base class(03h), and the devices
> with 0x00h sub-class code are VGA devices. VGA devices with programmin
On 07/10/2023 00:38, Kuogee Hsieh wrote:
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver during
generic_edp_panel_probe() due to AUX DPCD read failed at edp panel driver.
Incorporate PM runtime framework into
Currently eDP population is done at msm_dp_modeset_init() which happen
at binding time. Move eDP population to be done at display probe time
so that probe deferral cases can be handled effectively.
wait_for_hpd_asserted callback is added during drm_dp_aux_init()
to ensure eDP's HPD is up before pro
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
bridge.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver during
generic_edp_panel_probe() due to AUX DPCD read failed at edp panel driver.
Incorporate PM runtime framework into DP driver so that host controller's
power
Original both parser->parse() and dp_power_client_init() are done at
dp_display_bind() since eDP population is done at binding time.
In the preparation of having eDP population done at probe() time,
move both function from dp_display_bind() to dp_display_probe().
Changes in v6:
-- move dp_power_cl
EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
DP host controller. Since external DP host controller initialization had
been incorporated into pm_runtime_resume(), this flag became obsolete.
msm_dp_irq_postinstall() which triggers EV_HPD_INIT_SETUP event is
obsoleted accor
The is_connected flag is set to true after DP mainlink successfully
finishes link training to enter into ST_MAINLINK_READY state rather
than being set after the DP dongle is connected. Rename the
is_connected flag with link_ready flag to match the state of DP
driver's state machine.
Changes in v5:
The purpose of this patch series is to incorporate pm runtime framework
into MSM eDP/DP driver so that eDP panel can be detected by DRM eDP panel
driver during system probe time. During incorporating procedure, original
customized pm realted fucntions, such as dp_pm_prepare(), dp_pm_suspend(),
dp_p
Currently the dp_display_request_irq() is executed at msm_dp_modeset_init()
which ties irq registering to the DPU device's life cycle, while depending on
resources that are released as the DP device is torn down. Move register DP
driver irq handler to dp_display_probe() to have dp_display_irq_handl
Hi Kees,
On Fri, Oct 06, 2023 at 01:17:45PM -0700, Kees Cook wrote:
> Prepare for the coming implementation by GCC and Clang of the __counted_by
> attribute. Flexible array members annotated with __counted_by can have
> their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
> array
On Fri, 6 Oct 2023 at 23:44, Kuogee Hsieh wrote:
>
>
> On 10/6/2023 11:04 AM, Dmitry Baryshkov wrote:
> > On 06/10/2023 19:42, Kuogee Hsieh wrote:
> >>
> >> On 10/6/2023 4:56 AM, Dmitry Baryshkov wrote:
> >>> On 04/10/2023 19:26, Kuogee Hsieh wrote:
> Currently DP driver is executed independe
On Thu, Oct 05, 2023 at 01:16:32PM +, Simon Ser wrote:
> The driver might pull connectors which weren't submitted by
> user-space into the atomic state. For instance,
> intel_dp_mst_atomic_master_trans_check() pulls in connectors
> sharing the same DP-MST stream. However, if the connector is
>
On 10/6/23 22:17, Kees Cook wrote:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE
On 10/6/2023 11:04 AM, Dmitry Baryshkov wrote:
On 06/10/2023 19:42, Kuogee Hsieh wrote:
On 10/6/2023 4:56 AM, Dmitry Baryshkov wrote:
On 04/10/2023 19:26, Kuogee Hsieh wrote:
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected
Delete the v86d netlink only after all the VBE tasks have been
completed.
Fixes initial state restore on module unload:
uvesafb: VBE state restore call failed (eax=0x4f04, err=-19)
Signed-off-by: Jorge Maidana
---
drivers/video/fbdev/uvesafb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
uvesafb_exec() is a static function defined and called only in
drivers/video/fbdev/uvesafb.c, remove the prototype from
include/video/uvesafb.h.
Fixes the warning:
./include/video/uvesafb.h:112:12: warning: 'uvesafb_exec' declared 'static' but
never defined [-Wunused-function]
when including '' i
Hi John,
> The latest GuC has new features and new workarounds that we wish to
> enable. So let the universe know that it is useful to update their
> firmware.
>
> Signed-off-by: John Harrison
Reviewed-by: Andi Shyti
Andi
On Mon, Sep 18, 2023 at 01:34:08PM +, Justin Stitt wrote:
> `strncpy` is deprecated for use on NUL-terminated destination strings [1].
>
> We should prefer more robust and less ambiguous string interfaces.
>
> A suitable replacement is `strscpy_pad` due to the fact that it
> guarantees NUL-te
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
A
On 06.10.2023 10:31, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
XeHP SDV was a pre-production hardware used to bring up ATS and was not
generally available. Since latter was since explicitly added, there is no
need to keep the code for the former around.
Signed-off-by: Tvrtko Ursulin
---
dr
On 06.10.2023 10:31, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
PVC support will not be coming to i915 so get rid of its partial
enablement and reduce the driver maintenance burden.
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i9
On 06.10.2023 10:31, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It is not our policy to keep pre-production hardware support for this long
so I guess this one was just forgotten.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/i915_dri
On 9/12/23 20:33, Zanoni, Paulo R wrote:
On Mon, 2023-09-11 at 14:47 +0200, Thomas Hellström wrote:
Add a motivation for and description of asynchronous VM_BIND operation
v2:
- Fix typos (Nirmoy Das)
- Improve the description of a memory fence (Oak Zeng)
- Add a reference to the document in t
Hi,
On Fri, Oct 6, 2023 at 3:12 AM Christian König wrote:
> When the operation busy waits then that *should* get accounted to the
> CPU time of the current process. When the operation sleeps and waits for
> some interrupt for example it should not get accounted.
> What you suggest is to put the p
On Fri, Oct 06, 2023 at 10:03:33AM +0200, David Hildenbrand wrote:
> > + *
> > + * Returns number of pages pinned. This would be equal to the number of
> > + * pages requested.
> > + * If nr_pages is 0 or negative, returns 0. If no pages were pinned,
> > returns
> > + * -errno.
> > + */
> > +long
Thanks Lukasz for the patch, looks like it is reviewed by.
@dan...@ffwll.ch or @airl...@gmail.com
, could any of you ack this as well, so I can go ahead
and push this to drm-misc-fixes branch?
Regards
Manasi
On Thu, Oct 5, 2023 at 6:35 AM Lukasz Majczak wrote:
> wt., 26 wrz 2023 o 16:01 Rado
On 06/10/2023 19:42, Kuogee Hsieh wrote:
On 10/6/2023 4:56 AM, Dmitry Baryshkov wrote:
On 04/10/2023 19:26, Kuogee Hsieh wrote:
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver
during
generic_edp_panel_pro
On Wed, 4 Oct 2023 at 19:27, Kuogee Hsieh wrote:
>
> Currently DP driver is executed independent of PM runtime framework.
> This leads msm eDP panel can not being detected by edp_panel driver during
> generic_edp_panel_probe() due to AUX DPCD read failed at edp panel driver.
> Incorporate PM runti
From: Rob Clark
ssh logging is the default for mesa, as it is generally more reliable.
But if there are kernel issues, especially at boot, UART logging is
infinitely more useful.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/ci/gitlab-ci.yml | 6 ++
1 file changed, 6 insertions(+)
diff --g
On Fri, 6 Oct 2023 at 19:26, Luca Weiss wrote:
>
> On Freitag, 6. Oktober 2023 15:38:51 CEST Dmitry Baryshkov wrote:
> > On 29/09/2023 23:52, Luca Weiss wrote:
> > > On Samstag, 23. September 2023 23:49:10 CEST Dmitry Baryshkov wrote:
> > >> Experimental support for MSM8953, which has MDP5 v1.16.
On 10/6/23 16:35, Maxime Ripard wrote:
> Hi Jocelyn,
>
> On Thu, Oct 05, 2023 at 11:16:15AM +0200, Jocelyn Falempe wrote:
>> On 05/10/2023 10:18, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Tue, Oct 03, 2023 at 04:22:45PM +0200, Jocelyn Falempe wrote:
diff --git a/include/drm/drm_drv.h b/inclu
On 10/6/2023 4:56 AM, Dmitry Baryshkov wrote:
On 04/10/2023 19:26, Kuogee Hsieh wrote:
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver
during
generic_edp_panel_probe() due to AUX DPCD read failed at edp p
From: Ajit Pal Singh
Device and Host have a time synchronization mechanism that happens once
during boot when device is in SBL mode. After that, in mission-mode there
is no timesync. In an experiment after continuous operation, device time
drifted w.r.t. host by approximately 3 seconds per day. T
AIC100 supports a timesync mechanism that allows AIC100 to timestamp
device logs with a host based time. This becomes useful for putting host
logs in a unified timeline with device logs for debugging and performance
profiling. The mechanism consists of a boot-time initialization and a
runtime perod
From: Pranjal Ramajor Asha Kanojiya
Use QAIC_TIMESYNC MHI channel to send UTC time to device in SBL
environment. Remove support for QAIC_TIMESYNC MHI channel in AMSS
environment as it is not used in that environment.
Signed-off-by: Pranjal Ramajor Asha Kanojiya
Reviewed-by: Jeffrey Hugo
Review
On Freitag, 6. Oktober 2023 15:38:51 CEST Dmitry Baryshkov wrote:
> On 29/09/2023 23:52, Luca Weiss wrote:
> > On Samstag, 23. September 2023 23:49:10 CEST Dmitry Baryshkov wrote:
> >> Experimental support for MSM8953, which has MDP5 v1.16. It looks like
> >> trimmed down version of MSM8996. Less S
On 06.10.2023 17:07, Michael Tretter wrote:
> I tested the i.MX8M Nano EVK with the NXP supplied MIPI-DSI adapter,
> which uses an ADV7535 MIPI-DSI to HDMI converter. I found that a few
> modes were working, but in many modes my monitor stayed dark.
>
> This series fixes the Samsung DSIM bridge dri
On Fri, 2023-10-06 at 09:31 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> It is not our policy to keep pre-production hardware support for this long
> so I guess this one was just forgotten.
Wouldn't it make sense to also remove the PCI IDs if they never made it
to the real production
From: Carl Vanderlip
Several virtualization use-cases either don't support 32 MultiMSIs
(Xen/VMware) or have significant drawbacks to their use (KVM's vIOMMU,
which is required to support 32 MSI, needs to allocate an alternate
system memory space for each device using vIOMMU (e.g. 8GB VM mem and
On 10/3/2023 12:42 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
Fix a bug on some platforms where FLR causes complete system
hang when CPU is low power states (C8 or above).
Why does FLR cause a complete system hang? Why does avoiding d0i3 fix
the issue? Feels like there could be a
The pull request you sent on Fri, 6 Oct 2023 14:58:38 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-10-06
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4940c1543b4381a4895072489b4de7b6145694f5
Thank you!
--
Deet-doot-dot, I am a bot.
https://ko
On Fri, Oct 06, 2023 at 08:59:15AM +0100, Tvrtko Ursulin wrote:
>
> On 05/10/2023 05:13, Luben Tuikov wrote:
> > On 2023-10-04 23:33, Matthew Brost wrote:
> > > On Tue, Sep 26, 2023 at 11:32:10PM -0400, Luben Tuikov wrote:
> > > > Hi,
> > > >
> > > > On 2023-09-19 01:01, Matthew Brost wrote:
> >
I tested the i.MX8M Nano EVK with the NXP supplied MIPI-DSI adapter,
which uses an ADV7535 MIPI-DSI to HDMI converter. I found that a few
modes were working, but in many modes my monitor stayed dark.
This series fixes the Samsung DSIM bridge driver to bring up a few more
modes:
The driver read th
From: Marco Felsch
Since the MIPI configuration can be changed on demand it is very useful
to print more MIPI settings during the MIPI device attach step.
Signed-off-by: Marco Felsch
Reviewed-by: Adam Ford #imx8mm-beacon
Tested-by: Adam Ford #imx8mm-beacon
Reviewed-by: Inki Dae
Acked-by: I
Calculating the byte_clk in kHz is imprecise for a hs_clock of 55687500
Hz, which may be used with a pixel clock of 74.25 MHz with mode
1920x1080-30.
Fix the calculation by using HZ instead of kHZ.
This requires to change the type to u64 to prevent overflows of the
integer type.
Reviewed-by: Ada
The PLL requires a clock frequency in a certain platform-dependent range
after the pre-divider. The reference clock for the PLL may change due to
changes to it's parent clock. Thus, the frequency may be out of range or
unsuited for generating the high speed clock for MIPI DSI.
Try to keep the pre-
The PLL reference clock may change at runtime when its parent clock
changes. For example, this may happen on the i.MX8M Nano if the
reference clock is a child of the Video PLL. If the pixel clock changes,
this may propagate to the Video PLL and as a side effect change the
reference clock. Thus, rea
Rounding the porches up instead of down fixes the samsung-dsim at
some more resolutions and refresh rates:
The following resolutions are working with rounded-up porches, but don't
work when the porches are rounded down:
1920x1080-59.94
1920x1080-30.00
1920x1080-29.97
1920x1080-25.00
1680x1050-59.
On 03/10/2023 04:21, Richard Acayan wrote:
The Snapdragon 670 uses similar clocks (with one frequency added) to the
Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
with configuration from the Pixel 3a downstream kernel.
Since revision 4.0 is SDM845, reuse some configuration
On 23/07/21 01:15PM, Fedor Pchelkin wrote:
> Inside drm_mode_setcrtc() connector_set is allocated using kmalloc_array()
> so its values are uninitialized. When filling this array with actual
> pointers to drm connector objects, an error caused with invalid ioctl
> request data may occur leading us
From: John Harrison
The latest GuC has new features and new workarounds that we wish to
enable. So let the universe know that it is useful to update their
firmware.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8
1 file changed, 4 insertions(+), 4 deleti
Hi,
On Thu, Oct 05, 2023 at 11:04:20AM +0200, Thomas Zimmermann wrote:
> DRM's format-conversion helpers require temporary memory. Pass the
> buffer from the caller and keep it allocated over several calls. Allow
> the caller to preallocate the buffer memory.
I'm sorry... but why? Why do you need
On Friday 06 October 2023, Helge Deller wrote:
> On 10/5/23 09:01, Zhang Shurong wrote:
> > Add missing pci_disable_device() in error path in ark_pci_probe().
>
> Do you have this hardware and tested your patch?
> I'm sure there is a reason, why "pci_disable_device()" was commented
> out in the or
Hi Jocelyn,
On Thu, Oct 05, 2023 at 11:16:15AM +0200, Jocelyn Falempe wrote:
> On 05/10/2023 10:18, Maxime Ripard wrote:
> > Hi,
> >
> > On Tue, Oct 03, 2023 at 04:22:45PM +0200, Jocelyn Falempe wrote:
> > > diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
> > > index 89e2706cac56..e538
Now that the driver core allows for struct class to be in read-only
memory, we should make all 'class' structures declared at build time
placing them into read-only memory, instead of having to be dynamically
allocated at runtime.
This requires some passing of const struct class * around in the co
Hi,
On Thu, Oct 5, 2023 at 7:20 PM Inki Dae wrote:
>
> Thanks for testing. :)
>
> Acked-by : Inki Dae
Inki: does that mean you'd like this to go through drm-misc? I'm happy
to do that, but there are no dependencies here so this could easily go
through your tree.
> 2023년 9월 22일 (금) 오후 3:00, Ma
Experimental support for MSM8917, which has MDP5 v1.15. It looks like
trimmed down version of MSM8937. Even fewer PP, LM and no DSI1.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 190 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 1 +
Experimental support for MSM8953, which has MDP5 v1.16. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 221 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
Experimental support for MSM8937, which has MDP5 v1.14. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 213 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
Extend DPU driver with experimental support for even more MDP5
platforms: MSM8937, MSM8917, MSM8953.
As with other MDP5 devices, one has to pass `msm.prefer_mdp5=false`
kernel param to test DPU driver insead of using MDP5.
Note, Luca Weiss has reported timeout issues with CMD panels. This is
not
On 29/09/2023 23:52, Luca Weiss wrote:
On Samstag, 23. September 2023 23:49:10 CEST Dmitry Baryshkov wrote:
Experimental support for MSM8953, which has MDP5 v1.16. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Hi Dmitry,
As written on IRC, on sdm632
From: Konrad Dybcio
Add support for MSM8996, which - fun fact - was the SoC that this driver
(or rather SDE, its downstream origin) was meant for and first tested on.
It has some hardware that differs from the modern SoCs, so not a lot of
current structs could have been reused. It's also seeming
Older (mdp5) platforms do not use per-SoC compatible strings. Instead
they use a single compat entry 'qcom,mdss'. To facilitate migrating
these platforms to the DPU driver provide a way to generate the MDSS /
UBWC data at runtime, when the DPU driver asks for it.
It is not possible to generate thi
Bring in hardware support for the SDM660 and SDM630 platforms, which
belong to the same DPU generation as MSM8998.
Note, by default these platforms are still handled by the MDP5 driver
unless the `msm.prefer_mdp5=false' parameter is provided.
Co-developed-by: Konrad Dybcio
Signed-off-by: Konrad
For some of the platforms (e.g. SDM660, SDM630, MSM8996, etc.) it is
possible to support this platform via the DPU driver (e.g. to provide
support for DP, multirect, etc). Add a modparam to be able to switch
between these two drivers.
All platforms supported by both drivers are by default handled
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
register regions are a part of the parent, MDSS device. Add support for
handling this binding differences.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
Over the last several years the DPU driver has been actively developed,
while the MDP5 is mostly in the maintenance mode. This results in some
features being available only in the DPU driver. For example, bandwidth
scaling, writeback support, properly supported bonded DSI aka dual DSI
support.
All
Hi Tvrtko,
On Fri, Oct 06, 2023 at 09:31:03AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> XeHP SDV was a pre-production hardware used to bring up ATS and was not
> generally available. Since latter was since explicitly added, there is no
mmhh?
> need to keep the code for the former
From: Nirmoy Das
Add a function for ratelimitted debug print.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Nirmoy Das
Signed-off-by: Andi Shyti
---
include/drm/drm_print
After folding QSEED3LITE and QSEED4 feature bits into QSEED3 several
VIG feature masks became equal. Drop these duplicates.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h| 2 +-
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 8
.../
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In order to simplify the driver
codepath, merge these th
As the subblock info is now mostly gone, inline and drop the macro
DPU_HW_SUBBLK_INFO.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 40 ++-
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/g
In order to check whether the SSPP block has scaler and CSC subblocks
the funcion dpu_plane_atomic_check_pipe() uses macros which enumerate
all possible scaler and CSC features. Replace those checks with the
scaler and CSC subblock length checks in order to be able to drop those
two macros.
Sugges
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +--
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 16 +--
.../msm/disp/dpu1/catalog/dpu_5_
From: Marijn Suijten
This pointer callback is never used and should be removed.
Signed-off-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
[DB: dropped the helpers completely, which are unused now]
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
In preparation to deduplicating SSPP subblocks, drop the (unused)
`smart_dma_priority' field from struct dpu_sspp_sub_blks. If it is
needed later (e.g. for SmartDMA v1), it should be added to the SSPP
declarations themselves.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
.../gp
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