Calculating the byte_clk in kHz is imprecise for a hs_clock of 55687500
Hz, which may be used with a pixel clock of 74.25 MHz with mode
1920x1080-30.
Fix the calculation by using HZ instead of kHZ.
This requires to change the type to u64 to prevent overflows of the
integer type.
Reviewed-by: Adam Ford <aford...@gmail.com> #imx8mm-beacon
Tested-by: Adam Ford <aford...@gmail.com> #imx8mm-beacon
Tested-by: Frieder Schrempf <frieder.schre...@kontron.de> # Kontron BL i.MX8MM
+ Waveshare 10.1inch HDMI LCD (E)
Reviewed-by: Marco Felsch <m.fel...@pengutronix.de>
Signed-off-by: Michael Tretter <m.tret...@pengutronix.de>
---
Changes in v2: None
---
drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index 714e1e833606..63a0d8dbe37c 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -986,10 +986,12 @@ static void samsung_dsim_set_display_mode(struct
samsung_dsim *dsi)
u32 reg;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
- int byte_clk_khz = dsi->hs_clock / 1000 / 8;
- int hfp = DIV_ROUND_UP((m->hsync_start - m->hdisplay) *
byte_clk_khz, m->clock);
- int hbp = DIV_ROUND_UP((m->htotal - m->hsync_end) *
byte_clk_khz, m->clock);
- int hsa = DIV_ROUND_UP((m->hsync_end - m->hsync_start) *
byte_clk_khz, m->clock);
+ u64 byte_clk = dsi->hs_clock / 8;
+ u64 pix_clk = m->clock * 1000;
+
+ int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) *
byte_clk, pix_clk);
+ int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) *
byte_clk, pix_clk);
+ int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) *
byte_clk, pix_clk);
/* remove packet overhead when possible */
hfp = max(hfp - 6, 0);
--
2.39.2
