On Wed, Feb 08, 2023 at 07:54:50AM -0800, Tom Rix wrote:
> Building with clang W=2 has several similar warnings
> drivers/accel/habanalabs/common/decoder.c:46:51: error: declaration shadows a
> variable in the global scope [-Werror,-Wshadow]
> static void dec_error_intr_work(struct hl_device *hdev
On Sun, 12 Feb 2023 at 00:43, Chris Clayton wrote:
>
>
>
> On 10/02/2023 19:33, Linux regression tracking (Thorsten Leemhuis) wrote:
> > On 10.02.23 20:01, Karol Herbst wrote:
> >> On Fri, Feb 10, 2023 at 7:35 PM Linux regression tracking (Thorsten
> >> Leemhuis) wrote:
> >>>
> >>> On 08.02.23 09
Hello,
syzbot found the following issue on:
HEAD commit:0983f6bf2bfc Merge tag 'devicetree-fixes-for-6.2-2' of git..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=134dab4d48
kernel config: https://syzkaller.appspot.com/x/.config?x=9e55e71813900595
das
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
between commits:
877f26bf3ca6 ("drm/amd/display: disable S/G display on DCN 2.1.0")
077e9659581a ("drm/amd/display: disable S/G display on DCN 3.1.2/3")
7ece674cd946 ("R
From: Dafna Hirschfeld
The cpu accessible dma allocations use the gen_pool api which actually
does not allocate new memory from the system but manages memory already
allocated before. When tracing this together with real dma
allocation/free it cause confusing logs like a '0' dma address and
a cpu
From: Dafna Hirschfeld
in the out_err flow, combine the two cases of soft-reset since
they have mostly common code. In addition unlock reset_info.lock
after touching reset count.
Signed-off-by: Dafna Hirschfeld
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/
From: Dafna Hirschfeld
Because this field is only used for debug print,
we can do more precise debug directly instead.
Signed-off-by: Dafna Hirschfeld
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/device.c | 13 +
1 file changed, 5 insert
From: Ohad Sharabi
The policy file of the events reset has been modified.
This change is reflected in the autogenerated file.
Signed-off-by: Ohad Sharabi
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
.../gaudi2/gaudi2_async_ids_map_extended.h| 488 +-
1 file cha
From: Dafna Hirschfeld
Align assignment of reset_upon_device_release to the convention used
in this function.
Signed-off-by: Dafna Hirschfeld
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/device.c | 7 +++
1 file changed, 3 insertions(+), 4 delet
From: Ofir Bitton
In order for interrupt timestamp to be more accurate we should
capture it during the interrupt handling rather than in threaded
irq context.
Signed-off-by: Ofir Bitton
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/habanalabs.h | 2 +
From: Tomer Tayar
"eq_base[eq->ci].hdr.ctl" is used directly in a print without a
le32_to_cpu() conversion.
Signed-off-by: Tomer Tayar
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/irq.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
d
From: Tal Cohen
We prefer not to handle the user interrupt job inside the interrupt
context. Instead, use threaded IRQ to handle the user interrupts.
This will allow to avoid disabling interrupts when the user process
registers for a new event and to avoid long handling inside an
interrupt.
Sign
From: Koby Elbaz
To match their description above the function
Signed-off-by: Koby Elbaz
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/security.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/accel/habanalabs/commo
From: Tomer Tayar
hl_irq_handler_default() is not used and can be removed.
Signed-off-by: Tomer Tayar
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/habanalabs.h | 1 -
drivers/accel/habanalabs/common/irq.c| 18 --
2 files cha
From: Ofir Bitton
In order to allow TPC engines to raise an assert, we must expose
the relevant MSIX interrupt to the user so he will configure the engine
correctly. In addition, we implement the corresponding interrupt
handler that will notify the user upon such an event.
Signed-off-by: Ofir Bi
From: Moti Haimovski
This commit minimizes the "chain of errors" displayed when memory
mapping fails.
Signed-off-by: Moti Haimovski
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/memory.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
From: Koby Elbaz
In case a compute reset has failed or a request for a hard reset has
just arrived, then we escalate current reset procedure from compute
to hard-reset.
In such a case, the FW should be aware of the updated error cause,
and if LKD is the one who performs the reset (rather than the
From: Koby Elbaz
Required to allow the TPC compiler to know on which offset of the index
space it works on.
Signed-off-by: Koby Elbaz
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/gaudi2/gaudi2_security.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/
From: Tomer Tayar
When user closes the compute device file descriptor without closing a
dma-buf file descriptor, the device will be considered as in use,
leading to hard reset and killing the user process, to ensure the
release of the dma-buf.
Same thing will happen if user first releases the com
From: Tomer Tayar
The graceful reset mechanism is currently enabled only for reset
requests that will end up with hard-reset.
In future, reset requests due to errors in some device engines, are
going to be modified to request compute-reset, as the much longer
hard-reset is not really needed there
From: Tomer Tayar
When user closes the device file descriptor, it is checked whether the
device is still in use, and a message is printed if it is.
To make this message more informative, add to this print also the reason
due to which the device is considered as in use.
The possible reasons which
From: Moti Haimovski
Enhance the existing user notifications by adding a HW and FW critical
event bits to be used when a HW or FW event occur that requires
both SW abort and hard-resetting the chip.
Signed-off-by: Moti Haimovski
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers
From: Ofir Bitton
In order for engine cores to raise interrupts towards FW, They need
to know which register the event data should be written to.
Hence, we forward the relevant scratchpad register received during
dynamic regs handshake with FW.
Signed-off-by: Ofir Bitton
Reviewed-by: Oded Gabba
From: Dani Liberman
PSOC RAZWI handling code did not took into account single router that
supports several initiators with different XY coordinates. Also, it
ignored XY_HI coordinate. This caused 2 problems:
1. RAZWI handle ignored some initiators.
2. When getting PSOC RAZWI from some routers, th
It is more concise than to pass it to device init. Once we will add the
accel class, then we won't need to change the function signatures.
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/device.c | 16
drivers/accel/habanalabs/common/habanalabs.h | 4
From: Tomer Tayar
The same mutex lock/unlock and counter decrementing in
hl_release_dmabuf() is already done in the memhash_node_export_put()
helper function.
Signed-off-by: Tomer Tayar
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/memory.c | 89
Make it easier to later add support for accel device.
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/debugfs.c | 129 --
1 file changed, 68 insertions(+), 61 deletions(-)
diff --git a/drivers/accel/habanalabs/common/debugfs.c
b/drivers/accel/habanalabs/commo
Move the cdev creation code from the main hdev init function to
a separate function. This will make the code more readable once we
add the accel registration code (instead/in addition to legacy
cdev).
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/device.c | 49 --
From: Koby Elbaz
RAZWI handling routine is called from most EQ events,
no matter if a RAZWI happens or not.
This fix is added to verify the handler is called only if
a real RAZWI indication in HW has been detected.
Signed-off-by: Koby Elbaz
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
From: Ofir Bitton
Currently we support scenarios where a timestamp registration request
of a certain offset is received during the interrupt handling of the
same offset. In this case we give a grace period of up to 100us for
the interrupt handler to finish.
It seems that sometimes the interrupt h
Hello,
On Sun, Feb 12, 2023 at 06:52:05PM +0100, Frank Oltmanns wrote:
> Hi Ondřej,
> hi Guido,
>
> Ondřej, thank you very much for your feedback!
>
> I have a couple of questions.
>
> Ondřej Jirman writes:
>
> > On Sun, Feb 12, 2023 at 01:08:29PM +0100, Frank Oltmanns wrote:
> >> In contrast
Hi Ondřej,
hi Guido,
Ondřej, thank you very much for your feedback!
I have a couple of questions.
Ondřej Jirman writes:
> On Sun, Feb 12, 2023 at 01:08:29PM +0100, Frank Oltmanns wrote:
>> In contrast to the JH057N panel, the XBD599 panel does not require a 20
>> msec delay after initializatio
This patch fixes flickering after resume from sleep on panel
xingbangda,xbd599 (e.g. used in PinePhone).
It was originally submitted by Ondrej Jirman in July 2020:
https://lore.kernel.org/all/20200716123753.3552425-1-meg...@megous.com/
The original patchset contained two patches. This submission
This patch fixes intermittent panel initialization failures and screen
corruption during resume from sleep on panel xingbangda,xbd599 (e.g.
used in PinePhone).
It was originally submitted by Ondrej Jirman in July 2020:
https://lore.kernel.org/all/20200716123753.3552425-1-meg...@megous.com/
The or
In contrast to the JH057N panel, the XBD599 panel does not require a 20
msec delay after initialization and exiting sleep mode. Therefore, move
the delay into the already existing device specific initialization
function.
Also, the timing contraints after entering and exiting sleep mode differ
betw
From: Ondrej Jirman
Switching to a different reset sequence, enabling IOVCC before enabling
VCC.
There also needs to be a delay after enabling the supplies and before
deasserting the reset. The datasheet specifies 1ms after the supplies
reach the required voltage. Use 10-20ms to also give the po
Hi Thomas,
On 2/9/23 05:55, Thomas Zimmermann wrote:
> Get the kernel's global video= parameter with fb_get_option(). Done
> to unexport the internal fbdev state fb_mode_config. No functional
> changes.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/ps3/ps3av.c | 11 +--
> 1 file
On 12/02/2023 05:08, Liu Ying wrote:
> Add BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
> compatible string. The panel has a LVDS display interface.
>
> The panel's product specification can be found at:
> http://www.onetech.com.tw/files/EV121WXM-N10-1850ProductSpecification_20180801
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_brid
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++-
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Ba
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshk
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/bridge
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
Reviewed-by: Daniel Vetter
---
drivers/gpu/
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
Hi,
On 1/18/22 20:00, Yaroslav Bolyukin wrote:
Add a brief commit message, describing a user-visible effect of this
patch. Tell that this change prevents exposing headset as a regular
display to the system, while it will work with SteamVR.
> Signed-off-by: Yaroslav Bolyukin
> ---
> drivers/gpu
On Sun, Feb 12, 2023 at 01:08:29PM +0100, Frank Oltmanns wrote:
> In contrast to the JH057N panel, the XBD599 panel does not require a 20
> msec delay after initialization and exiting sleep mode. Therefore, move
> the delay into the already existing device specific initialization
> function.
>
> A
Hi Frank,
Thanks for giving this another spin!
On Sat, Feb 11, 2023 at 06:17:47PM +0100, Frank Oltmanns wrote:
> This patch fixes intermittent panel initialization failures and screen
> corruption during resume from sleep on panel xingbangda,xbd599 (e.g.
> used in PinePhone).
>
> It was original
From: "Mike Rapoport (IBM)"
There are several architectures that duplicate definitions of
map_page_into_agp(), unmap_page_from_agp() and flush_agp_cache().
Define those in asm-generic/agp.h and use it instead of duplicated
per-architecture headers.
Signed-off-by: Mike Rapoport (IBM)
---
arch/
From: "Mike Rapoport (IBM)"
There is a copy of alloc_gatt_pages() and free_gatt_pages in several
architectures in arch/$ARCH/include/asm/agp.h. All the copies do exactly
the same: alias alloc_gatt_pages() to __get_free_pages(GFP_KERNEL) and
alias free_gatt_pages() to free_pages().
Define alloc_g
From: "Mike Rapoport (IBM)"
Hi,
asm/agp.h is duplicated in several architectures, with x86 being the
only instance that differs from the rest.
Introduce asm-generic/agp.h and use it instead of per-architecture
headers for the most cases.
I believe that asm-generic is the best tree to pick up t
60 matches
Mail list logo
