Here I introduced is_error to judge if the ppgtt_invalidate_spt is
called from good case or not. Only free spt in good case, leave it to
handle for the error path of caller.
Zheng Hacker 于2022年9月16日周五 14:39写道：
>
> From 8d95c1399e3ff345500a575e21254a73b0c89144 Mon Sep 17 00:00:00 2001
> From: xmzy
>From 8d95c1399e3ff345500a575e21254a73b0c89144 Mon Sep 17 00:00:00 2001
From: xmzyshypnc <1002992...@qq.com>
Date: Fri, 16 Sep 2022 14:37:48 +0800
Subject: [PATCH] drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry
There is a double-free security bug in split_2MB_gtt_entry.
Here is a callin
From: Minghao Chi
The implementation of strscpy() is more robust and safer.
That's now the recommended way to copy NUL terminated strings.
Signed-off-by: Minghao Chi
---
drivers/dma-buf/dma-buf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma-buf/dma-buf.c b/d
The sequence for Source DP PHY CTS automation is [2][1]:
1- Emulate successful Link Training(LT)
2- Short HPD and change link rates and number of lanes by LT.
(This is same flow for Link Layer CTS)
3- Short HPD and change PHY test pattern and swing/pre-emphasis
levels (This step should not trigger
On Thu, Sep 15, 2022 at 05:45:46PM -0700, Chia-I Wu wrote:
> On Thu, Sep 15, 2022 at 4:14 AM Dan Carpenter
> wrote:
> >
> > The ->ring_idx_mask variable is a u64 so static checkers, Smatch in
> > this case, complain if the BIT() is not also a u64.
> >
> > drivers/gpu/drm/virtio/virtgpu_ioctl.c:50
From: José Roberto de Souza
Expand the current stepping convention to accommodate the GMD
stepping info. Typically GMD step maps to letter stepping
by "A + step %4" and number to "A + step /4" i.e, GMD step
0 maps to STEP_A0, 1 to _A1, 2 to _A2, 3 to _A3, 4 to STEP_B0...
Future platforms might b
From: Matt Roper
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
From: Matt Roper
The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.
For render/compute engines, the part of the context
The PCI Id's and platform definition are posted earlier.
Handful of early enablement patches including support for
display power wells, VBT and AUX Channel mapping, PCH and
gmbus support, dbus, mbus, sagv and memory bandwidth support
got merged.
This series adds the support for a new way to read G
Although the bspec lists several MMIO ranges as "MSLICE," it turns out
that a subset of these are of a "GAM" subclass that has unique rules and
doesn't followed regular mslice steering behavior.
* Xe_HP SDV: GAM ranges must always be steered to 0,0. These
registers share the regular steering
Hi Lucas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on bb4f6b2281b11b009210f62eecd291f7b75c1e85]
url:
https://github.com/intel-lab-lkp/linux/commits/Lucas-De-Marchi/drm-i915-Improvements-to-stolen-memory-setup/20220916-044155
base: bb4f6b2281b11b009210
On Thu, Sep 15, 2022 at 4:14 AM Dan Carpenter wrote:
>
> The ->ring_idx_mask variable is a u64 so static checkers, Smatch in
> this case, complain if the BIT() is not also a u64.
>
> drivers/gpu/drm/virtio/virtgpu_ioctl.c:50 virtio_gpu_fence_event_create()
> warn: should '(1 << ring_idx)' be a 64
Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on bb4f6b2281b11b009210f62eecd291f7b75c1e85]
url:
https://github.com/intel-lab-lkp/linux/commits/Lucas-De-Marchi/drm-i915-Improvements-to-stolen-memory-setup/20220916-044155
base: bb4f6b2281b11b009210f62eec
Hi Lucas,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v6.0-rc5 next-20220915]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
On Thu, Sep 15, 2022 at 03:25:15PM +0300, Jani Nikula wrote:
> On Wed, 14 Sep 2022, Matt Roper wrote:
> > Now that MTL is going to start providing two GTs, there are a few more
> > places in the driver that need to iterate over each GT instead of
> > operating directly on gt0. Also some more deli
From: Tvrtko Ursulin
This, along with the changes already landed in commit 1c66a12ab431
("drm/i915: Handle each GT on init/release and suspend/resume") makes
engines from all GTs actually known to the driver.
To accomplish this we need to sprinkle a lot of for_each_gt calls around
but is otherwi
From: Tvrtko Ursulin
Walk all GTs when suspending.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
From: Tvrtko Ursulin
Walk all GTs from i915_gem_resume when resuming engines.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(
Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0. Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.
From: Chris Wilson
If we abort driver initialisation in the middle of gt/engine discovery,
some engines will be fully setup and some not. Those incompletely setup
engines only have 'engine->release == NULL' and so will leak any of the
common objects allocated.
v2:
- Drop the destroy_pinned_cont
Add some helpers: adjust_stolen(), request_smem_stolen_() and
init_reserved_stolen() that are now called by i915_gem_init_stolen() to
initialize each part of the Data Stolen Memory region. Main goal is to
split the reserved part, also known as WOPCM, as its calculation changes
often per platform.
On 15/09/2022 18:18, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
On Fri, 16 Sept 2022 at 00:25, Bjorn Andersson wrote:
>
> On Tue, Sep 13, 2022 at 12:45:45PM +0200, Sebastian Reichel wrote:
> > Hi,
> >
> > [+Cc Lee Jones, DRI devel]
> >
> > On Tue, Aug 09, 2022 at 10:05:00PM -0500, Bjorn Andersson wrote:
> > > The Qualcomm Snapdragon-based Lenovo Yoga C630 has
Hi Jani,
On Thu, Sep 15, 2022 at 03:25:15PM +0300, Jani Nikula wrote:
> On Wed, 14 Sep 2022, Matt Roper wrote:
> > Now that MTL is going to start providing two GTs, there are a few more
> > places in the driver that need to iterate over each GT instead of
> > operating directly on gt0. Also some
Hi Matt,
On Wed, Sep 14, 2022 at 03:04:26PM -0700, Matt Roper wrote:
> From: Tvrtko Ursulin
>
> Walk all GTs when suspending.
>
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
I had this as well... thanks again!
Reviewed-by: Andi Shyti
Andi
Hi Matt,
On Wed, Sep 14, 2022 at 03:04:25PM -0700, Matt Roper wrote:
> From: Tvrtko Ursulin
>
> Walk all GTs from i915_gem_resume when resuming engines.
>
> Cc: Andi Shyti
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
I had this (and others) in my multi-gt branch from a long t
On Tue, Sep 13, 2022 at 12:45:45PM +0200, Sebastian Reichel wrote:
> Hi,
>
> [+Cc Lee Jones, DRI devel]
>
> On Tue, Aug 09, 2022 at 10:05:00PM -0500, Bjorn Andersson wrote:
> > The Qualcomm Snapdragon-based Lenovo Yoga C630 has some sort of EC
> > providing AC-adapter and battery status, as well
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 6ce5d01e7011b32600656bf90a626b1e51fb192a Add linux-next specific
files for 20220915
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209150141.wgbakqmx-...@intel.com
https
Reviewed-by: Caz Yokoyama
Better to be safe.
On Thu, Sep 15, 2022 at 1:40 PM Lucas De Marchi
wrote:
> DSMBASE register is defined so BDSM bitfield contains the bits 63 to 20
> of the base address of stolen. For the supported platforms bits 0-19 are
> zero but that may not be true in future. A
> On Wed, Sep 14, 2022 at 04:51:03PM +, Winkler, Tomas wrote:
> > >
> > > On DG2, HuC loading is performed by the GSC, via a PXP command. The
> > > load operation itself is relatively simple (just send a message to
> > > the GSC with the physical address of the HuC in LMEM), but there are
>
Hi Michel,
First of all, thanks a lot for your review. I want to take this
opportunity to discuss this topic in more depth and learn more from you
and others.
+(Nick, Leo, Daniel, Mark, Dave, Sean, Simon)
On 2022-09-15 04:55, Michel Dänzer wrote:
On 2022-09-14 22:08, Alex Hung wrote:
On 20
DSMBASE register is defined so BDSM bitfield contains the bits 63 to 20
of the base address of stolen. For the supported platforms bits 0-19 are
zero but that may not be true in future. Add the missing mask.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
Reduce possible side effects of assigning the region and bailing out due
to errors.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index acc561c0f0aa..42f4769bb4ac 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem
There is no reason to consider the setup of Data Stolen Memory fatal on
dgfx and non-fatal on integrated. Move the debug and error propagation
around so both have the same behavior: non-fatal. Before this change,
loading i915 on a system with TGL + DG2 would result in just TGL
succeeding the initia
Add some helpers: adjust_stolen(), request_smem_stolen_() and
init_reserved_stolen() that are now called by i915_gem_init_stolen() to
initialize each part of the Data Stolen Memory region. Main goal is to
split the reserved part, also known as WOPCM, as its calculation changes
often per platform.
: bb4f6b2281b11b009210f62eecd291f7b75c1e85
change-id: 20220915-stolen-7aa0e407368f
Best regards,
--
Lucas De Marchi
On 9/15/2022 01:59, Tvrtko Ursulin wrote:
Hi,
On 15/09/2022 00:46, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This p
Hi Lucas,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v6.0-rc5 next-20220915]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
On Thu, Sep 15, 2022, at 8:17 PM, kernel test robot wrote:
> Hi Arnd,
> tree:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 3245cb65fd91cd514801bf91f5a3066d562f0ac4
> commit: 3d427228f7370894680580fcd0381c0349624fa1 ARM: ixp4xx: enable
> multiplatform
On Wed, 14 Sep 2022 16:33:22 +0200, Geert Uytterhoeven wrote:
> Convert the NXP TDA998x HDMI transmitter Device Tree binding
> documentation to json-schema.
>
> Add missing "#sound-dai-cells" property.
> Add ports hierarchy, as an alternative to port.
> Drop pinctrl properties, as they do not belo
On 2022-09-15 17:53, Hugh Cole-Baker wrote:
On 15 Sep 2022, at 15:40, Robin Murphy wrote:
On 2021-10-19 22:58, Hugh Cole-Baker wrote:
Define the memory region on RK3399 VOPs containing the gamma LUT at
base+0x2000.
Signed-off-by: Hugh Cole-Baker
---
Changes from v1: no changes in this patch
> On 15 Sep 2022, at 15:40, Robin Murphy wrote:
>
> On 2021-10-19 22:58, Hugh Cole-Baker wrote:
>> Define the memory region on RK3399 VOPs containing the gamma LUT at
>> base+0x2000.
>> Signed-off-by: Hugh Cole-Baker
>> ---
>> Changes from v1: no changes in this patch
>> arch/arm64/boot/dts/r
Due to i915_perf assuming that it can use the i915_gem_context reference
to protect its i915->gem.contexts.list iteration, we need to defer removal
of the context from the list until last reference to the context is put.
However, there is a risk of triggering kernel warning on contexts list not
emp
From: Chris Wilson
i915_perf assumes that it can use the i915_gem_context reference to
protect its i915->gem.contexts.list iteration. However, this requires
that we do not remove the context from the list until after we drop the
final reference and release the struct. If, as currently, we remove
i915_perf assumes that it can use the i915_gem_context reference to
protect its i915->gem.contexts.list iteration. However, this requires
that we do not remove the context from the list until after we drop the
final reference and release the struct. If, as currently, we remove the
context from the
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver abt-y030xx067a has no spi_device_id for abt,y030xx067a
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-abt-y030xx067a.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warnings:
SPI driver panel-ilitek-ili9322 has no spi_device_id for dlink,dir-685-panel
SPI driver panel-ilitek-ili9322 has no spi_device_id for ilitek,ili9322
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-ilitek-
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver nt39016 has no spi_device_id for kingdisplay,kd035g6-54nt
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-novatek-nt39016.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver nv3052c has no spi_device_id for leadtek,ltk035c5444t
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/d
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver panel-innolux-ej030na has no spi_device_id for innolux,ej030na
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-innolux-ej030na.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/driver
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver ws2401-panel has no spi_device_id for samsung,lms380kf01
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-widechips-ws2401.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver panel-samsung-s6e63m0 has no spi_device_id for samsung,s6e63m0
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/dr
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver s6d27a1-panel has no spi_device_id for samsung,s6d27a1
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-samsung-s6d27a1.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/dr
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver tpo-tpg110-panel has no spi_device_id for tpo,tpg110
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-tpo-tpg110.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/panel
From: Wei Yongjun
Add spi_device_id entries to silent following SPI warning:
SPI driver db7430-panel has no spi_device_id for samsung,lms397kf04
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/panel/panel-samsung-db7430.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/d
Hi Jason,
On 15/09/2022 03:24, Jason-JH Lin wrote:
Hi Matthias,
Thanks for the reviews.
On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with th
On 14/09/2022 15:21, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add mmsys func to manipulate dpi output format config for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
Reviewed-by: Nís F. R. A. Prado
Applied, thanks!
---
drivers/soc/me
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
Am 15.09.22 um 15:02 schrieb Yadav, Arvind:
On 9/15/2022 5:37 PM, Christian König wrote:
Is that sufficient to allow running a desktop on amdgpu with the
extra check enabled? If yes that would be quite a milestone.
Yes, It is running on amdgpu with extra config enabled.
In this case I will
On 15/09/2022 09:50, Bo-Chen Chen wrote:
Warning:
../drivers/gpu/drm/mediatek/mtk_dp.c: In function ‘mtk_dp_video_mute’:
../drivers/gpu/drm/mediatek/mtk_dp.c:947:23: warning: format ‘%x’
expects argument of type ‘unsigned int’, but argument 4 has type ‘long
unsigned int’ [-Wformat=]
947 |
On 15/09/2022 09:50, Bo-Chen Chen wrote:
Some definitions in mtk_dp_reg.h are not used, so remove these
redundant codes.
Signed-off-by: Bo-Chen Chen
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/driver
On Wed, Sep 14, 2022 at 03:35:30PM +0200, Sascha Hauer wrote:
> On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote:
> > On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote:
> > > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote:
> > > > Hi,
> > > >
> > > > On 9/12/
G200ER does not seem to support 24 bpp, so force the console to
use 32 bpp. The problem was introduced, when commit 73f54d5d9682
("drm/mgag200: Remove special case for G200SE with <2 MiB") changed
the preferred color depth from 32 bit to 24 bit.
A setting of 24 is the correct color depth, but G200
Hi,
> Hi
>
> Am 14.09.22 um 16:58 schrieb Wang Yugui:
> [...]
> >> 24-bit works on my G200HE and G200 test machines. Maybe the G200ER has a
> >> bug.
> >>
> >> When I try 16-bit depth, the display works, but is way too dark. No
> >> fiddling with the LUT tables fixes this. It's 90s hardware, so
On 2021-10-19 22:58, Hugh Cole-Baker wrote:
Define the memory region on RK3399 VOPs containing the gamma LUT at
base+0x2000.
Signed-off-by: Hugh Cole-Baker
---
Changes from v1: no changes in this patch
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 de
Hi Lucas,
On Do, 2022-09-15 at 16:19 +0200, Lucas Stach wrote:
> While the interface for the MMU mapping takes phys_addr_t to hold a
> full 64bit address when necessary and MMUv2 is able to map physical
> addresses with up to 40bit, etnaviv_iommu_map() truncates the address
> to 32bits. Fix this b
On 15/09/2022 12:50, Dmitry Baryshkov wrote:
> On 11/09/2022 22:19, Krzysztof Kozlowski wrote:
>> On 11/09/2022 20:36, Krzysztof Kozlowski wrote:
>>
If your child schema fails, the referencing schema fails as well...
>>>
>>>
>>> Although now with DSI-PHY I cannot reproduce it and I am pretty s
While the interface for the MMU mapping takes phys_addr_t to hold a
full 64bit address when necessary and MMUv2 is able to map physical
addresses with up to 40bit, etnaviv_iommu_map() truncates the address
to 32bits. Fix this by using the correct type.
Fixes: 931e97f3afd8 ("drm/etnaviv: mmuv2: sup
Hey all, I'd be interested in having the pr-tracker-bot [1] set up for
the drm subsystem, following the dri-devel mailing list [2] and
notifying when the pull requests have been merged to either the drm-next
or drm-fixes branches of the main drm repository [3].
What would this require in terms o
On Thu, Sep 15, 2022 at 12:15:28PM +0100, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Thu, Sep 15, 2022 at 10:26 AM Krzysztof Kozlowski
> wrote:
> > On Wed, 14 Sep 2022 16:33:22 +0200, Geert Uytterhoeven wrote:
> > > Convert the NXP TDA998x HDMI transmitter Device Tree binding
> > > document
Hi Dave and Daniel,
Nothing that big for this round, but a couple targeting stable.
Here goes drm-intel-fixes-2022-09-15:
- Revert a display patch around max DP source rate now
that the proper WaEdpLinkRateDataReload is in place. (Ville)
- Fix perf limit reasons bit position. (Ashutosh)
- Fix
On Tue, 19 Oct 2021 22:58:40 +0100, Hugh Cole-Baker wrote:
> This extends the Rockchip VOP driver to support setting the gamma LUT on the
> RK3399 SoC. Previously, the driver supported gamma control for the RK3288
> only. On the RK3399 the method for updating the LUT is slightly different.
> This i
On Sat, 21 May 2022 15:07:16 -0400, Tom Rix wrote:
> cppcheck reports
> [drivers/gpu/drm/rockchip/rockchip_drm_vop.c:186]: (style) The function
> 'vop_writel' is never used.
>
> vop_writel is static function that is not used, so remove it.
Applied, thanks!
[1/1] drm/rockchip: remove vop_writel
On Tue, 19 Oct 2021 22:58:40 +0100, Hugh Cole-Baker wrote:
> This extends the Rockchip VOP driver to support setting the gamma LUT on the
> RK3399 SoC. Previously, the driver supported gamma control for the RK3288
> only. On the RK3399 the method for updating the LUT is slightly different.
> This i
Add missing device nodes (DSI, PHYs, DP/eDP) to the existing MDSS
schemas.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/qcom,msm8998-mdss.yaml| 12 +
.../display/msm/qcom,qcm2290-mdss.yaml| 6 +
.../display/msm/qcom,sc7180-mdss.yaml
Move properties common to all MDSS DT nodes to the mdss-common.yaml.
This extends qcom,msm8998-mdss schema to allow interconnect nodes, which
will be added later, once msm8998 gains interconnect support.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-msm8998.yaml | 41 +---
Move properties common to all DPU DT nodes to the dpu-common.yaml.
Note, this removes description of individual DPU port@ nodes. However
such definitions add no additional value. The reg values do not
correspond to hardware INTF indices. The driver discovers and binds
these ports not paying any ca
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8250 platform.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/mdss-common.yaml | 4 +-
.../bindings/display/msm/qcom,sm8250-dpu.yaml | 92
.../display/msm/qcom,sm8250-mdss.yaml
In order to make the schema more readable, split dpu-sc7280 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7280.yaml | 162 --
.../bindings/display/msm/qcom,sc7280-dpu.yaml |
In order to make the schema more readable, split dpu-qcm2290 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-qcm2290.yaml | 148 --
.../display/msm/qcom,qcm2290-dpu.yaml |
In order to make the schema more readable, split dpu-msm8998 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-msm8998.yaml | 150 --
.../display/msm/qcom,msm8998-dpu.yaml |
In order to make the schema more readable, split dpu-sc7180 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7180.yaml | 158 --
.../bindings/display/msm/qcom,sc7180-dpu.yaml |
In order to make the schema more readable, split dpu-sdm845 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sdm845.yaml | 148 --
.../bindings/display/msm/qcom,sdm845-dpu.yaml |
Add gcc-bus clock required for the SDM845 DPU device tree node. This
change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845:
move bus clock to mdp node for sdm845 target"), but was not reflected in
the schema.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../devic
Split Mobile Display SubSystem (MDSS) root node bindings to the separate
yaml file. Changes to the existing (txt) schema:
- Added optional "vbif_nrt_phys" region used by msm8996
- Made "bus" and "vsync" clocks optional (they are not used by some
platforms)
- Added (optional) "core" clock adde
Add interconnects required for the SDM845 MDSS device tree node. This
change was made in the commit c8c61c09e38b ("arm64: dts: qcom: sdm845:
Add interconnects property for display"), but was not reflected in the
schema.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-
Create separate YAML schema for MDSS devicesd$ (both for MDP5 and DPU
devices). Cleanup DPU schema files, so that they do not contain schema
for both MDSS and DPU nodes. Apply misc small fixes to the DPU schema
afterwards. Add schema for the MDSS and DPU on sm8250 platform.
Changes since v6:
- Re
>-Original Message-
>From: Dmitry Osipenko
>Sent: Tuesday, September 13, 2022 3:28 PM
>To: David Airlie ; Gerd Hoffmann ;
>Gurchetan Singh ; Chia-I Wu
>; Daniel Vetter ; Daniel Almeida
>; Gert Wollny ;
>Gustavo Padovan ; Daniel Stone
>; Tomeu Vizoso ;
>Maarten Lankhorst ; Maxime Ripard
>;
On 9/15/2022 5:37 PM, Christian König wrote:
Is that sufficient to allow running a desktop on amdgpu with the extra
check enabled? If yes that would be quite a milestone.
Yes, It is running on amdgpu with extra config enabled.
What's left is checking the userspace IGT tests. Especially the
Hi
Am 14.09.22 um 16:58 schrieb Wang Yugui:
[...]
24-bit works on my G200HE and G200 test machines. Maybe the G200ER has a bug.
When I try 16-bit depth, the display works, but is way too dark. No fiddling
with the LUT tables fixes this. It's 90s hardware, so it should support 16-bit
framebuff
On 08/09/2022 00:13, Dmitry Baryshkov wrote:
On Wed, 7 Sept 2022 at 22:59, Rob Herring wrote:
On Thu, Sep 01, 2022 at 01:23:04PM +0300, Dmitry Baryshkov wrote:
Move properties common to all DPU DT nodes to the dpu-common.yaml.
Note, this removes description of individual DPU port@ nodes. How
On Thu, Sep 01, 2022 at 03:47:06PM +0300, Jani Nikula wrote:
> Prefer the parsed results for is_hdmi in display info over calling
> drm_detect_hdmi_monitor().
>
> Cc: Thierry Reding
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/tegra/hdmi.c | 9 +
On Wed, 14 Sep 2022, Matt Roper wrote:
> Now that MTL is going to start providing two GTs, there are a few more
> places in the driver that need to iterate over each GT instead of
> operating directly on gt0. Also some more deliberate cleanup is needed,
> in cases where we fail GT/engine initiali
On Wed, Sep 07, 2022 at 11:38:41AM +0300, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> Hi all,
>
> this series adds support for Host1x context isolation
> on Tegra234 (Orin). The difference from previous generations
> is that there are two IOMMUs to which engines can be attached
> to, resu
Is that sufficient to allow running a desktop on amdgpu with the extra
check enabled? If yes that would be quite a milestone.
What's left is checking the userspace IGT tests. Especially the
sync_file and drm_syncobj tests I would expect to have problems with
this extra check.
Thanks,
Christi
Am 14.09.22 um 18:43 schrieb Arvind Yadav:
Fence signaling must be enabled to make sure that
the dma_fence_is_signaled() function ever returns true.
Since drivers and implementations sometimes mess this up,
this ensures correct behaviour when DMABUF_DEBUG_ENABLE_SIGNALING
is used during debugging
Am 14.09.22 um 18:43 schrieb Arvind Yadav:
dma_fence_wait() should always enable signaling even
when the fence is already signaled.
Signed-off-by: Arvind Yadav
Reviewed-by: Christian König
---
Changes in v1..v3: This new patch was not part of previous series.
---
drivers/dma-buf/dma-f
Hi Dave and Daniel,
this is the drm-misc-fixes PR for this week.
Best regards
Thomas
drm-misc-fixes-2022-09-15:
Short summary of fixes pull:
* gma500: Locking and IRQ fixes
* meson: OSD1 display fixes
* panel-edp: Fix Innolux timings
* rockchip: DP/HDMI fixes
The following changes since com
On Mon, 29 Aug 2022, Jani Nikula wrote:
> Hi Dave & Daniel -
>
> drm-intel-next-2022-08-29:
> drm/i915 feature pull for v6.1:
Hey, I started making another pull request, but realized you haven't
pulled this one yet. Anything the matter, or just fell between the
cracks?
BR,
Jani.
>
> Features a
On 11/09/2022 22:19, Krzysztof Kozlowski wrote:
On 11/09/2022 20:36, Krzysztof Kozlowski wrote:
If your child schema fails, the referencing schema fails as well...
Although now with DSI-PHY I cannot reproduce it and I am pretty sure I
reproduced it with DPU controllers after modifying the DT
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