On Mon, Aug 29, 2022 at 08:46:42PM +0200, Noralf Trønnes wrote:
> Something has gone wrong with this patchset, there are double line endings.
I noticed this, too, and I think the reason is because these patches were
generated with "b4 send -o", but actually sent using git-send-email. It's not
a us
Send DP_SET_POWER_D3 command to the downstream before stopping DP, so the
suspend process will not be interrupted by the HPD interrupt. Also modify
the order in .atomic_enable callback to make the callbacks symmetric.
Fixes: 46ca7da7f1e8 ("drm/bridge: it6505: Send DPCD SET_POWER to downstream")
Si
From: ChiaEn Wu
MediaTek MT6370 is a SubPMIC consisting of a single cell battery charger
with ADC monitoring, RGB LEDs, dual channel flashlight, WLED backlight
driver, display bias voltage supply, one general purpose LDO, and the
USB Type-C & PD controller complies with the latest USB Type-C and
From: Alice Chen
The MediaTek MT6370 is a highly-integrated smart power management IC,
which includes a single cell Li-Ion/Li-Polymer switching battery
charger, a USB Type-C & Power Delivery (PD) controller, dual Flash
LED current sources, a RGB LED driver, a backlight WLED driver,
a display bias
From: ChiYuan Huang
The MediaTek MT6370 is a highly-integrated smart power management IC,
which includes a single cell Li-Ion/Li-Polymer switching battery
charger, a USB Type-C & Power Delivery (PD) controller, dual
Flash LED current sources, a RGB LED driver, a backlight WLED driver,
a display b
From: ChiaEn Wu
MediaTek MT6370 is a SubPMIC consisting of a single cell battery charger
with ADC monitoring, RGB LEDs, dual channel flashlight, WLED backlight
driver, display bias voltage supply, one general purpose LDO, and the
USB Type-C & PD controller complies with the latest USB Type-C and
From: ChiaEn Wu
MediaTek MT6370 is a SubPMIC consisting of a single cell battery charger
with ADC monitoring, RGB LEDs, dual channel flashlight, WLED backlight
driver, display bias voltage supply, one general purpose LDO, and the
USB Type-C & PD controller complies with the latest USB Type-C and
From: ChiaEn Wu
Add linear_range_idx macro for declaring the linear_range struct simply.
Signed-off-by: ChiaEn Wu
---
v9
- Revise LINEAR_RANGE() and LINEAR_RANGE_IDX()
---
include/linux/linear_range.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/linux/linear_range.
From: ChiYuan Huang
Add MT6370 backlight binding documentation.
Reviewed-by: Rob Herring
Reviewed-by: Daniel Thompson
Signed-off-by: ChiYuan Huang
Signed-off-by: ChiaEn Wu
---
.../leds/backlight/mediatek,mt6370-backlight.yaml | 121 +
1 file changed, 121 insertions(+)
From: Alice Chen
Add MediaTek MT6370 flashlight binding documentation.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Alice Chen
Signed-off-by: ChiaEn Wu
---
.../bindings/leds/mediatek,mt6370-flashlight.yaml | 41 ++
1 file changed, 41 insertions(+)
create mode 100644
From: ChiYuan Huang
Add MediaTek MT6370 current sink type LED indicator binding documentation.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: ChiYuan Huang
Signed-off-by: ChiaEn Wu
---
.../bindings/leds/mediatek,mt6370-indicator.yaml | 81 ++
1 file changed, 81 inserti
From: ChiaEn Wu
Add MediaTek MT6370 Charger binding documentation.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: ChiaEn Wu
---
.../power/supply/mediatek,mt6370-charger.yaml | 88 ++
1 file changed, 88 insertions(+)
create mode 100644
Documentation/devicetree/bindi
From: ChiaEn Wu
This patch series add MediaTek MT6370 PMIC support and add a index macro
to . The MT6370 is a highly-integrated smart power
management IC, which includes a single cell Li-Ion/Li-Polymer switching
battery charger, a USB Type-C & Power Delivery (PD) controller, dual
Flash LED curren
DSI interface used with a bridge chip connected to an external
display is subject to the same pixel clock limits as one
which is natively pluggable like DisplayPort.
Hence filter out DSI modes having an unsupported pixel clock
if its connected to a bridge which is pluggable.
Ideally, this can be
Add maximum external pixel clock for all targets based on
the advertised limits for each of them.
The pixel clock has been calculated from the timings mentioned
in the CEA specification for CEA modes and according to
the VESA CVT standard for the others.
Signed-off-by: Abhinav Kumar
---
drivers
Filter out DP/eDP modes having an unsupported pixel clock by
replacing the current hard-coded limit with the per chipset advertised
value.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 ---
drivers/gpu/drm/msm/dp/dp_display.c | 16 +---
drivers
As reported on https://gitlab.freedesktop.org/drm/msm/-/issues/17, currently
there is no mechanism to limit the display output to the pluggable displays
and it lets users connect any monitor on any chipset based device.
This can lead to undefined behavior because lets say the display
advertises an
Hi Prabhakar,
Thank you for the patch.
On Mon, Aug 29, 2022 at 10:58:16PM +0100, Lad Prabhakar wrote:
> With 'unevaluatedProperties' support implemented, there's a number of
> warnings when running dtbs_check:
>
> arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb:
> hdmi@
+Philipp
Quoting Akhil P Oommen (2022-08-28 12:21:13)
>
> Some clients like adreno gpu driver would like to ensure that its gdsc
> is collapsed at hardware during a gpu reset sequence. This is because it
> has a votable gdsc which could be ON due to a vote from another subsystem
> like tz, hyp et
With 'unevaluatedProperties' support implemented, there's a number of
warnings when running dtbs_check:
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb:
hdmi@fead: Unevaluated properties are not allowed ('resets' was unexpected)
From schema:
Documentation/dev
Hi,
On Mon, Aug 22, 2022 at 9:33 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Aug 18, 2022 at 8:03 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Aug 17, 2022 at 8:22 PM Hsin-Yi Wang wrote:
> > >
> > > On Thu, Aug 18, 2022 at 11:19 AM Rock Chiu
> > > wrote:
> > > >
> > > > How does T4/T5
Hi Oded (and sorry I misspelled your name last time),
Oded Gabbay writes:
> On Tue, Aug 23, 2022 at 9:24 PM Kevin Hilman wrote:
>>
>> Hi Obed,
>>
>> Oded Gabbay writes:
>>
>> [...]
>>
>> > I want to update that I'm currently in discussions with Dave to figure
>> > out what's the best way to mo
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL medi
On Thu, 25 Aug 2022 14:33:32 +0300, Krzysztof Kozlowski wrote:
> minItems, if missing, are implicitly equal to maxItems, so drop
> redundant piece to reduce size of code.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml | 1 -
> .../d
On Thu, 25 Aug 2022 15:54:10 +0300, Krzysztof Kozlowski wrote:
> On PM660L, PMI8994 and PMI8998, the WLED has two address spaces. This
> also fixes dtbs_check warnings like:
>
> arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dtb: leds@d800: reg:
> [[55296], [2]] is too long
>
> Signed-off-
On Thu, 25 Aug 2022 15:54:09 +0300, Krzysztof Kozlowski wrote:
> Document compatibles for QFPROM used on IPQ8064 and SDM630. They are
> compatible with generic QFPROM fallback.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 2 ++
> 1 fi
On Thu, 25 Aug 2022 14:33:34 +0300, Krzysztof Kozlowski wrote:
> minItems, if missing, are implicitly equal to maxItems, so drop
> redundant piece to reduce size of code.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 1 -
> .../d
On Thu, 25 Aug 2022 14:33:33 +0300, Krzysztof Kozlowski wrote:
> minItems, if missing, are implicitly equal to maxItems, so drop
> redundant piece to reduce size of code.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml | 1 -
> 1 file
On Thu, 25 Aug 2022 14:33:31 +0300, Krzysztof Kozlowski wrote:
> minItems, if missing, are implicitly equal to maxItems, so drop
> redundant piece to reduce size of code.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml | 1 -
> .../d
On Thu, 25 Aug 2022 14:33:30 +0300, Krzysztof Kozlowski wrote:
> minItems, if missing, are implicitly equal to maxItems, so drop
> redundant piece to reduce size of code.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../bindings/arm/socionext/socionext,uniphier-system-cache.yaml | 1 -
> 1 fi
On Tue, 23 Aug 2022 09:56:42 -0500, Rob Herring wrote:
> In order to ensure only documented properties are present, node schemas
> must have unevaluatedProperties or additionalProperties set to false
> (typically).
>
> Signed-off-by: Rob Herring
> ---
> Documentation/devicetree/bindings/display/
On Tue, 23 Aug 2022 13:10:31 +0300, Krzysztof Kozlowski wrote:
> reg-io-width is a standard property, so no need for defining its type
> with $ref.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml | 1 -
> 1 file changed, 1 deletion(
Applied. Thanks!
Alex
On Mon, Aug 29, 2022 at 8:29 AM wrote:
>
> From: Jinpeng Cui
>
> Return value from kfd_wait_on_events() and io_remap_pfn_range() directly
> instead of taking this in another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: Jinpeng Cui
> ---
> drivers/gp
Applied. Thanks!
Alex
On Mon, Aug 29, 2022 at 8:13 AM wrote:
>
> From: Jinpeng Cui
>
> Return value from expression directly instead of
> taking this in another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: Jinpeng Cui
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw
On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki wrote:
>
> The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
> with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
> range from BIT[18-13] and the upstream driver is using the same offset.
>
> However, offse
Thanks for this! We definitely need more logging like this in DRM. for patches
1 and 2:
Reviewed-by: Lyude Paul
On Mon, 2022-08-29 at 15:14 +, Simon Ser wrote:
> Sometimes drivers are missing logs when they return EINVAL.
> Printing the failure here in common code can help understand where
>
Den 29.08.2022 15.11, skrev Maxime Ripard:
> Since we've recently added a ton of tests, the list starts to be a bit
>
> of a mess and creates unneeded conflicts.
>
>
>
> Let's order it alphabetically.
>
>
>
> Signed-off-by: Maxime Ripard
>
>
>
Something has gone wrong with this patch
Samsung MIPI DSIM master can also be found in i.MX8MM SoC.
Add compatible and associated driver_data for it.
v4:
* none
v3:
* enable DSIM_QUIRK_FIXUP_SYNC_POL quirk
v2:
* collect Laurent r-b
v1:
* none
Reviewed-by: Laurent Pinchart
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsu
eLCDIF is expecting to have input_bus_flags as DE_LOW in order to
set active low during valid data transfer on each horizontal line.
Add DE_LOW flag via drm bridge timings.
v4, v3, v2:
* none
v1:
* none
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsung-dsim.c | 5 +
1 file chan
DSI host initialization handling in previous exynos dsi driver has
some pitfalls. It initializes the host during host transfer() hook
that is indeed not the desired call flow for I2C and any other DSI
configured downstream bridges.
Host transfer() is usually triggered for downstream DSI panels or
Explicit fixing up of mode_flags is required for DSIM present
in i.MX8M SoC.
At least the LCDIF + DSIM needs active low sync polarities in
order to correlate the correct sync flags of the surrounding
components in the chain to make sure the whole pipeline can
work properly.
So, add DSIM_QUIRK_FIX
Samsung MIPI DSIM bridge can also be found in i.MX8MM SoC.
Add dt-bingings for it.
v4:
* none
v3:
* collect Rob Acked-by
v2:
* updated comments
v1:
* new patch
Acked-by: Rob Herring
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 +
1 file
In i.MX8M Mini/Nano SoC the DSI Phy requires a MIPI DPHY bit
to reset in order to activate the PHY and that can be done via
upstream i.MX8M blk-ctrl driver.
So, mark the phy get as optional.
v4, v3, v2:
* none
v1:
* new patch
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsung-dsim.c
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
default RGB888_1X24 bus format on DSI-end.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component
The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
range from BIT[18-13] and the upstream driver is using the same offset.
However, offset 13 is not working on i.MX8M Mini platforms but downstream
NX
In order to make a common Samsung DSIM bridge driver some platform
specific glue code needs to maintain separately as it is hard to
maintain platform specific glue and conventional component_ops on
the drm bridge drivers side.
This patch is trying to support that glue code initialization based
on
This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.
Previous v2 can be available here [1].
The final bridge supports both the Exynos and i.MX8MM DSI devices.
On, summary this patch-set break the entire DSIM driver into
- platform specific g
The child devices in MIPI DSI can be binding with OF-graph
and also via child nodes.
The OF-graph interface represents the child devices via
remote and associated endpoint numbers like
dsi {
compatible = "fsl,imx8mm-mipi-dsim";
ports {
port@0 {
reg = <0>;
Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.
In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.
This patch is trying to differentiat
From: Marek Szyprowski
Restore the proper bridge chain by finding the previous bridge
in the chain instead of passing NULL.
This establishes a proper bridge chain while attaching downstream
bridges.
v4:
* none
v3:
* new patch
Signed-off-by: Marek Szyprowski
Signed-off-by: Jagan Teki
---
dr
Hi Laurent
On 8/26/2022 4:55 AM, Laurent Pinchart wrote:
Hello,
On Fri, Aug 26, 2022 at 01:17:43PM +0300, Dmitry Baryshkov wrote:
On 22/08/2022 19:31, Dmitry Baryshkov wrote:
On 09/08/2022 22:40, Laurent Pinchart wrote:
On Mon, Aug 08, 2022 at 05:35:30PM -0700, Abhinav Kumar wrote:
adv7533
Hi Dave,
On Fri, Jul 22, 2022 at 9:35 PM Dave Stevenson
wrote:
>
> Hi Jagan and Marek.
>
> On Fri, 22 Jul 2022 at 16:35, Marek Szyprowski
> wrote:
> >
> > On 20.07.2022 17:52, Jagan Teki wrote:
> > > Host transfer() in DSI master will invoke only when the DSI commands
> > > are sent from DSI de
Hi Biju,
Thank you for the patch.
On Mon, Aug 29, 2022 at 10:19:01AM +0100, Biju Das wrote:
> This driver supports the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI video mode only.
>
> Signed-off-by: Biju Das
> Acked-by: Sam Ravnborg
> ---
> v5->v6:
> * Updated commit
adv7533 bridge tries to dynamically switch lanes based on the
mode by detaching and attaching the mipi dsi device.
This approach is incorrect because this method of dynamic switch of
detaching and attaching the mipi dsi device also results in removing
and adding the component which is not necessar
Hi Biju,
On Mon, Aug 29, 2022 at 04:26:02PM +, Biju Das wrote:
> Hi Robert,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> >
> > Hey Biju,
> >
> > The patch does not apply on drm-misc-next, could you rebase it and
> > submit the next ve
Moving the locking for MMIO debug (and the final check for unclaimed
accesses when resuming debug after a userspace-initiated forcewake) will
make it simpler to completely skip MMIO debug handling on uncores that
don't support it in future patches.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile
We're slowly transitioning the init-time kzalloc's of the driver over to
DRM-managed allocations; let's make sure the uncore objects allocated
for non-root GTs are thus allocated.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++
1 file changed, 2 insertions(+), 4 dele
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and just point the media GT's
instance at the same
Top-level handling of standalone media interrupts will be processed as
part of the primary GT's interrupt handler (since primary and media GTs
share an MMIO space, unlike remote tile setups). When we get down to
the point of handling engine interrupts, we need to take care to lookup
VCS and VECS e
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL medi
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i9
The original intent of intel_uncore_mmio_debug as described in commit
0a9b26306d6a ("drm/i915: split out uncore_mmio_debug") was to be a
singleton structure that could be shared between multiple GTs' uncore
objects in a multi-tile system. Somehow we went off track and
started allocating separate i
Starting with MTL, media functionality has moved into a new, second GT
at the hardware level. This new GT, referred to as "standalone media"
in the spec, has its own GuC, power management/forcewake, etc. The
general non-engine GT registers for standalone media start at 0x38,
but otherwise use
Hi,
On Wed, Aug 24, 2022 at 6:00 AM Tomi Valkeinen
wrote:
>
> From: Laurent Pinchart
>
> Implement the bridge connector-related .get_edid() and .detect()
> operations, and report the related bridge capabilities and type.
>
> These ops are only added for DP mode. They should also be used for eDP
Hi,
On Wed, Aug 24, 2022 at 6:00 AM Tomi Valkeinen
wrote:
>
> From: Tomi Valkeinen
>
> The blanking related registers are 8 bits, so reject any modes
> with larger blanking periods.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 +++
>
On 8/29/22 16:54, Robert Foss wrote:
Hey Marek,
Hi,
On Mon, 1 Aug 2022 at 15:18, Marek Vasut wrote:
The ICN6211 is capable of deriving its internal PLL clock from either
MIPI DSI HS clock, external REFCLK clock, or even internal oscillator.
Currently supported is only the first option. Add
Hi,
On Wed, Aug 24, 2022 at 6:01 AM Tomi Valkeinen
wrote:
>
> From: Tomi Valkeinen
>
> The driver does not check AUX_IRQ_STATUS_NAT_I2C_FAIL bit at all when
> sending AUX transfers,
It doesn't? What about a few lines down from where your patch modifies
that reads:
else if (val & AUX_IRQ_STAT
On Sat, Aug 27, 2022 at 03:03:43PM +0200, Vitaly Kuznetsov wrote:
> There are already three places in kernel which define PCI_VENDOR_ID_MICROSOFT
> and two for PCI_DEVICE_ID_HYPERV_VIDEO and there's a need to use these
> from core Vmbus code. Move the defines where they belong.
It's a minor annoya
Clang warns:
drivers/gpu/drm/msm/dsi/dsi_host.c:1903:14: error: variable 'device_node' is
uninitialized when used here [-Werror,-Wuninitialized]
of_node_put(device_node);
^~~
drivers/gpu/drm/msm/dsi/dsi_host.c:1870:44: note: initialize the variable
'de
On Fri, Aug 26, 2022 at 02:02:33PM -0700, Matt Roper wrote:
> This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a.
>
> The intent of Wa_14015141709 was to inform us that userspace can no
> longer control object-level preemption as it has on past platforms
> (i.e., by twiddling register bi
On 8/29/22 06:41, Hans de Goede wrote:
Hi,
On 8/26/22 00:21, Daniel Dadap wrote:
On 8/25/22 9:37 AM, Hans de Goede wrote:
On some new laptop designs a new Nvidia specific WMI interface is present
which gives info about panel brightness control and may allow controlling
the brightness through
Hi Robert,
Thanks for the feedback.
> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
>
> Hey Biju,
>
> The patch does not apply on drm-misc-next, could you rebase it and
> submit the next version?
I believe[1] is dependent on this patch series. Sorry for not
making it clear wh
On Fri, Aug 26, 2022 at 02:27:18PM -0700, Matt Roper wrote:
> On client DG2 platforms, optimal performance is achieved with the
> hardware's default "age based" thread execution setting. However on
> ATS-M, switching this to "round robin after dependencies" provides
> better performance. We'll ad
On Wed, 30 Mar 2022 at 21:39, Chris Morgan wrote:
>
> From: Chris Morgan
>
> Add the option to set the byteswap order in the devicetree. For the
> official HDMI DIP for the NTC CHIP the byteswap order needs to be
> RGB, however the driver sets it as BGR. With this patch the driver
> will remain a
Hey Chris,
Sorry about being slow getting to this.
On Wed, 30 Mar 2022 at 21:39, Chris Morgan wrote:
>
> From: Chris Morgan
>
> Update dt-binding documentation to add support for setting byteswap of
> chrontel ch7033.
>
> New property name of chrontel,byteswap added to set the byteswap order.
>
Hi Alvin,
Sorry about being slow to get to this series.
Can you rebase it on drm-misc-next and send out the next version?
On Sat, 19 Mar 2022 at 16:10, Alvin Šipraga wrote:
>
> From: Alvin Šipraga
>
> We have an ADV7535 which is nominally supported by this driver. These
> two patches fix up th
On Friday, August 26th, 2022 at 10:19, Ville Syrjälä
wrote:
> On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> > This new kernel capability indicates whether async page-flips are
> > supported via the atomic uAPI. DRM clients can use it to check
> > for support before feeding DRM_MOD
On Fri, 26 Aug 2022 at 20:57, Lucas Stach wrote:
>
> There are two events that signal a real change of the link state: HPD going
> high means the sink is newly connected or wants the source to re-read the
> EDID, RX sense going low is a indication that the link has been disconnected.
>
> Ignore th
Hey Biju,
The patch does not apply on drm-misc-next, could you rebase it and
submit the next version?
Additionally it has a few 'checkpatch --strict' warnings.
On Mon, 29 Aug 2022 at 11:19, Biju Das wrote:
>
> This driver supports the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently sup
Document flags accepted by the page-flip and atomic IOCTLs.
v2 (Pekka):
- Mention DRM_EVENT_FLIP_COMPLETE in DRM_MODE_PAGE_FLIP_EVENT docs.
- Expand DRM_MODE_ATOMIC_NONBLOCK and DRM_MODE_ATOMIC_ALLOW_MODESET
description.
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Pekka Paalanen
Cc: Ville
CC Ville for the ASYNC bits, see below.
On Friday, August 26th, 2022 at 10:53, Pekka Paalanen
wrote:
> > +/**
> > + * DRM_MODE_PAGE_FLIP_EVENT
> > + *
> > + * Request that the kernel sends back a vblank event (see
> > + * struct drm_event_vblank) when the page-flip is done.
>
> ...with type =
On Wed, 10 Aug 2022 at 11:27, Neil Armstrong wrote:
>
> On 01/08/2022 14:54, Marek Vasut wrote:
> > The drm_of_lvds_get_data_mapping() returns either negative value on
> > error or MEDIA_BUS_FMT_* otherwise. The check for 'ret' would also
> > catch the positive case of MEDIA_BUS_FMT_* and lead to
This can help figure out why the kernel returns EINVAL from
user-space.
v2: add missing newlines
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Lyude Paul
---
drivers/gpu/drm/drm_atomic_helper.c | 32 +++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a
This helps user-space understand why an atomic commit fails.
v2: new patch
Signed-off-by: Simon Ser
---
drivers/gpu/drm/drm_bridge.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
index 1545c50f
Sometimes drivers are missing logs when they return EINVAL.
Printing the failure here in common code can help understand where
EINVAL is coming from.
All other atomic_check() calls in this file already have similar
logging.
v2: add missing newlines
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc
Hi Stephen, Mike,
On Mon, Aug 15, 2022 at 05:31:22PM +0200, Maxime Ripard wrote:
> Those patches used to be part of a larger clock fixes series:
> https://lore.kernel.org/linux-clk/20220715160014.2623107-1-max...@cerno.tech/
>
> However, that series doesn't seem to be getting anywhere, so I've sp
Hey Marco,
Sorry about the slow reply.
This series no longer applies on drm-misc-next. Can you rebase this
series and send it out a v2?
Rob.
On Sat, 16 Jul 2022 at 10:13, Zheyu Ma wrote:
>
> When removing the module we will get the following warning:
>
> [ 31.911505] i2c-core: driver [stdp2690-ge-b850v3-fw] unregistered
> [ 31.912484] general protection fault, probably for non-canonical address
> 0xdc01: [#1] PREE
Sometimes drivers are missing logs when they return EINVAL.
Printing the failure here in common code can help understand where
EINVAL is coming from.
All other atomic_check() calls in this file already have similar
logging.
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Lyude Paul
---
drivers
This can help figure out why the kernel returns EINVAL from
user-space.
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Lyude Paul
---
drivers/gpu/drm/drm_atomic_helper.c | 32 +++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomi
Hi Marek,
On Mon, 25 Jul 2022 at 00:43, Marek Vasut wrote:
>
> Currently the driver only handles panel directly connected to the DPI output.
> Handle the case where a bridge is connected past DPI output of this bridge.
> This could be e.g. DPI to LVDS encoder chip.
>
> Signed-off-by: Marek Vasut
Hey Marek,
On Mon, 1 Aug 2022 at 15:18, Marek Vasut wrote:
>
> The ICN6211 is capable of deriving its internal PLL clock from either
> MIPI DSI HS clock, external REFCLK clock, or even internal oscillator.
> Currently supported is only the first option. Add support for external
> REFCLK clock inp
Hi Stan,
I wonder if it is better if you reorder the 3 and 4 patches in this - move this
4/4 before the 3rd
one and modify the 3rd one accordingly.
Also, instead of getting rid of limits, keep limits and populate the limits
according to dsc or
normal dp_mst. What do you think?
BR
vinod
On Mo
On Sat, 27 Aug 2022 at 03:10, Laurent Pinchart
wrote:
>
> Hi Tomi,
>
> On Wed, Aug 24, 2022 at 04:00:34PM +0300, Tomi Valkeinen wrote:
> > From: Laurent Pinchart
> >
> > Implement the bridge connector-related .get_edid() and .detect()
> > operations, and report the related bridge capabilities and
Nomodeset kernel parameter is for all graphics cards. Amdgpu cannot
be set separately in some scenarios, such as hybrid graphics(i + a).
Add modeset module parameter for amdgpu to set kernel mode separately.
Signed-off-by: Zhen Ni
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 -
1
On Mon, Aug 29, 2022 at 04:14:54PM +0200, Geert Uytterhoeven wrote:
> Hi Maxime,
>
> On Mon, Aug 29, 2022 at 3:30 PM Maxime Ripard wrote:
> > On Wed, Aug 24, 2022 at 06:42:18PM +0200, Mateusz Kwiatkowski wrote:
> > > - Speaking of closed captioning... a lot of different stuff were put in
> > > t
Reviewed-by: Vinod Govindapillai
On Mon, 2022-08-29 at 12:58 +0300, Stanislav Lisovskiy wrote:
> We currently always exit that bpp loop because drm_dp_atomic_find_vcpi_slots
> doesn't care if we actually can fit those or not.
> I think that wasn't the initial intention here, especially when
> we
On Tue, 23 Aug 2022, Jilin Yuan wrote:
> Delete the redundant word 'other'.
> Delete the redundant word 'the'.
> Delete the redundant word 'will'.
>
> Signed-off-by: Jilin Yuan
Doesn't apply because some of the hunks were already fixed by other
commits.
BR,
Jani.
> ---
> drivers/gpu/drm/i
Hi Matti,
On Fri, 19 Aug 2022 at 21:18, Matti Vaittinen wrote:
>
> Simplify drivers using managed "regulator get and enable".
>
> meson:
> Use the devm_regulator_get_enable_optional(). Also drop the seemingly
> unused struct member 'hdmi_supply'.
>
> sii902x:
> Simplify using devm_regulator_bulk_
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