Hi,
Maybe it would be a good idea to state the intended use-case in the
commit message? And explain why the current (driver-specific IIRC) APIs
aren't enough?
Since this introduces new uAPI, can you point to a user-space patch
which uses the new uAPI? See this link for more info on DRM user-space
|Acked-by: Nirmoy Das |
On 03/03/2022 11:02, Matthew Auld wrote:
Currently this will enforce both 2M alignment and padding for any LMEM
pages inserted into the GGTT. However, this was only meant to be applied
to the compact-pt layout with the ppGTT. For the GGTT we can reduce the
alignment and p
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about a GPU reset, and can also provide
some information like:
- process ID of the process involved with the GPU reset
- process name of the involved process
- the GPU status info (using flags)
This patch a
From: Shashank Sharma
This patch adds a work function, which sends a GPU reset
uevent and some contextual infomration, like the PID and
some status flags. This work should be scheduled during
a GPU reset.
The userspace can do some recovery and post-processing work
based on this event and informa
The Renesas RZ/V2L SoC (a.k.a R9A07G054) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documen
Hi Daniel:
On 3/9/22 10:03, Andy Yan wrote:
Hi Daniel:
On 3/8/22 22:04, Daniel Stone wrote:
On Tue, 8 Mar 2022 at 08:42, Andy Yan wrote:
On 3/7/22 21:09, Daniel Stone wrote:
On Mon, 7 Mar 2022 at 12:18, Andy Yan wrote:
When run a weston 10.0.0:
# export XDG_RUNTIME_DIR=/tmp
# wes
On Tue, Mar 8, 2022 at 6:00 PM Benjamin Gaignard
wrote:
>
>
> Le 08/03/2022 à 10:12, Hsin-Yi Wang a écrit :
> > On Fri, Mar 4, 2022 at 7:25 PM Benjamin Gaignard
> > wrote:
> >>
> >> Le 04/03/2022 à 11:15, xinlei@mediatek.com a écrit :
> >>> From: Xinlei Lee
> >>>
> >>> In upstream-v5.8, dsi_
From: Akeem G Abodunrin
When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on devices
of tgl+, HW does not care about certain register address offsets, but
instead check the following for valid address ranges on specific engines:
RCS && CCS: BITS(0 - 10)
BCS: BITS(0 - 1
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
cc: Joonas Lahtinen
Signed-off-by: Ramalingam
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson
Cc: Mik
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
From: Chris Wilson
The lrc_isolation test uses two contexts in order to read from one
context while poisoning from a second. The test verifies that the
writes of the second context do not leak into the first context. This is
done by first recording the register state from context A, forcing a
pre
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUS
From: Chris Wilson
Verify that one context running on engine A cannot manipulate another
client's context concurrently running on engine B using unprivileged
access.
Signed-off-by: Chris Wilson
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +-
From: Chris Wilson
Verify that context isolation is also preserved when accessing
context-local registers with relative-mmio commands.
Signed-off-by: Chris Wilson
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 --
1 file changed, 67 inserti
Patches that fix and enhance the selftest_lrc
Akeem G Abodunrin (1):
drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
Chris Wilson (7):
drm/i915/selftests: Exercise relative mmio paths to non-privileged
registers
drm/i915/selftests: Exercise cross-process context isolati
Hi Daniel:
On 3/8/22 22:04, Daniel Stone wrote:
On Tue, 8 Mar 2022 at 08:42, Andy Yan wrote:
On 3/7/22 21:09, Daniel Stone wrote:
On Mon, 7 Mar 2022 at 12:18, Andy Yan wrote:
When run a weston 10.0.0:
# export XDG_RUNTIME_DIR=/tmp
# weston --backend=drm-backend.so --use-pixma --tty
Hi Dave & Daniel,
Follow-up pull req for v5.18 to pull in some important fixes.
The following changes since commit afab9d91d872819f98a792c32c302d9e3261f1a1:
drm/msm/adreno: Expose speedbin to userspace (2022-02-25 13:29:57 -0800)
are available in the Git repository at:
https://gitlab.freed
On 3/8/22 2:57 PM, Nick Desaulniers wrote:
On Thu, Mar 3, 2022 at 12:19 PM wrote:
From: Tom Rix
Clang static analysis reports this issue
anx7625.c:876:13: warning: The left operand of '&' is
a garbage value
if (!(bcap & 0xOA01)) {
^
bcap is only set by a successful call
On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
wrote:
>
> Add memory shrinker and new madvise IOCTL to the VirtIO-GPU driver.
> Userspace (BO cache manager of Mesa driver) will mark BOs as "don't need"
> using the new IOCTL to let shrinker purge the marked BOs on OOM, thus
> shrinker will lower me
On Tue, Mar 8, 2022 at 3:36 PM Dmitry Osipenko
wrote:
>
> On 3/9/22 01:24, Rob Clark wrote:
> > On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
> > wrote:
> >>
> >> On 3/8/22 19:29, Rob Clark wrote:
> >>> On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
> >>> wrote:
>
> Hello,
>
> >
On 3/9/22 01:24, Rob Clark wrote:
> On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
> wrote:
>>
>> On 3/8/22 19:29, Rob Clark wrote:
>>> On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
>>> wrote:
Hello,
This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
>>>
On Sun, Mar 06, 2022 at 08:04:49PM +0200, Laurent Pinchart wrote:
> On Sun, Mar 06, 2022 at 07:39:03PM +0200, Laurent Pinchart wrote:
> > Add a new dt-bindings/media/video-interfaces.h header that defines
> > macros corresponding to the bus types from media/video-interfaces.yaml.
> > This allows av
t; In the optimized case, cfb_imageblit() is now ~2x faster than before.
>
> v3:
> * fix commit description (Pekka)
>
> Signed-off-by: Thomas Zimmermann
> Acked-by: Sam Ravnborg
> Reviewed-by: Javier Martinez Canillas
This patch landed recently in linux next-2022
On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
wrote:
>
> On 3/8/22 19:29, Rob Clark wrote:
> > On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
> > wrote:
> >>
> >> Hello,
> >>
> >> This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
> >> During OOM, the shrinker will release
Hi,
On 3/8/22 23:07, Harry Wentland wrote:
>
>
> On 2022-03-08 17:02, Hans de Goede wrote:
>> Hi,
>>
>> On 3/8/22 21:56, Sean Paul wrote:
>>> From: Sean Paul
>>>
>>> This patch adds the necessary hooks to make amdgpu aware of privacy
>>> screens. On devices with privacy screen drivers (such as
On 2022-03-08 17:02, Hans de Goede wrote:
> Hi,
>
> On 3/8/22 21:56, Sean Paul wrote:
>> From: Sean Paul
>>
>> This patch adds the necessary hooks to make amdgpu aware of privacy
>> screens. On devices with privacy screen drivers (such as thinkpad-acpi),
>> the amdgpu driver will defer probe u
Hi,
On 3/8/22 21:56, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds the necessary hooks to make amdgpu aware of privacy
> screens. On devices with privacy screen drivers (such as thinkpad-acpi),
> the amdgpu driver will defer probe until it's ready and then sync the sw
> and hw state on
On 3/8/22 17:21, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
On 3/8/22 14:49, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 02:27:40PM +0100, Marek Vasut wrote:
On 3/8/22 13:51, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wro
Am 2022-03-08 um 16:08 schrieb David Yat Sin:
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
Signed-off-by: David Yat Sin
Looks good to me. Please also post a link to the user mode change for this.
Note that the user mode code
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12
include/uapi/linux/kfd_ioctl.h | 3 ++-
2 files changed, 10 insertions(+), 5 dele
On Tue, 8 Mar 2022 at 21:48, Rob Clark wrote:
>
> From: Rob Clark
>
> Avoid going down devfreq paths on devices where devfreq is not
> initialized.
>
> v2: Change has_devfreq() logic [Dmitry]
>
> Reported-by: Linux Kernel Functional Testing
> Reported-by: Anders Roxell
> Signed-off-by: Rob Clar
From: Sean Paul
This patch adds the necessary hooks to make amdgpu aware of privacy
screens. On devices with privacy screen drivers (such as thinkpad-acpi),
the amdgpu driver will defer probe until it's ready and then sync the sw
and hw state on each commit the connector is involved and enabled.
Quoting Dmitry Baryshkov (2022-03-03 23:58:58)
> On Fri, 4 Mar 2022 at 07:31, Stephen Boyd wrote:
> >
> > Quoting Dmitry Baryshkov (2022-03-03 20:23:06)
> > > On Fri, 4 Mar 2022 at 01:32, Stephen Boyd wrote:
> > > >
> > > > Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> > > > > The only clock f
On 3/8/22 17:07, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> Currently the ssd130x driver only sets the segment remap setting when
> the device tree requests it; it however does not clear the setting if
> it is not requested. This leads to the setting incorrectly persisting
> if the hardware is
Quoting Dmitry Baryshkov (2022-03-03 19:21:06)
> MSM DRM driver already allows one to compile out the DP or DSI support.
> Add support for disabling other features like MDP4/MDP5/DPU drivers or
> direct HDMI output support.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Dmitry Baryshkov
> ---
R
Quoting Dmitry Baryshkov (2022-03-03 19:21:05)
> Let's make the match's data pointer a (sub-)driver's private data. The
> only user currently is the msm_drm_init() function, using this data to
> select kms_init callback. Pass this callback through the driver's
> private data instead.
>
> Signed-off
Quoting Dmitry Baryshkov (2022-03-03 19:21:04)
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 857eefbb8649..c89de88ed2d1 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -255,3 +258,170 @@ struct msm_mdss *msm_mdss_ini
Hello Chen-Yu,
Thanks a lot for your patch.
On 3/8/22 17:07, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The SSD130x's command to toggle COM scan direction uses bit 3 and only
> bit 3 to set the direction of the scanout. The driver has an incorrect
> GENMASK(3, 2), causing the setting to be se
Quoting Dmitry Baryshkov (2022-03-03 19:21:03)
> Since now there is just one mdss subdriver, drop all the indirection,
> make msm_mdss struct completely opaque (and defined inside msm_mdss.c)
> and call mdss functions directly.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Quoting Dmitry Baryshkov (2022-03-03 19:21:02)
> MDP5 and DPU1 both provide the driver handling the MDSS region, which
> handles the irq domain and (incase of DPU1) adds some init for the UBWC
> controller. Unify those two pieces of code into a common driver.
>
> Signed-off-by: Dmitry Baryshkov
>
Quoting Dan Carpenter (2022-03-07 05:31:05)
> These casts need to happen before the shift. The only time it would
> matter would be if "rev.core" is >= 128. In that case the sign bit
> would be extended and we do not want that.
>
> Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspac
Am 2022-03-08 um 14:11 schrieb David Yat Sin:
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
This deserves a minor version bump. The plugin should depend on that
bumped version when it starts using dmabuf handles for GTT BOs.
Re
Don't populate the read-only array ODValues on the stack but
instead make it static const. Also makes the object code a little
smaller.
Signed-off-by: Colin Ian King
---
drivers/video/fbdev/kyro/STG4000InitDevice.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video
Hi Doug,
Thank you for the patch.
On Tue, Mar 08, 2022 at 11:06:57AM -0800, Douglas Anderson wrote:
> The bindings for bridge chips should also get the same maintainers
> entry so the right people get notified about bindings changes.
>
> Signed-off-by: Douglas Anderson
Reviewed-by: Laurent Pin
Quoting Vinod Polimera (2022-03-08 08:54:56)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
How? I see ftbl_disp_cc_mdss_mdp_clk_src[] has multiple frequencies and
clk_rcg2_shared_ops so it doesn'
Protect concurrent access to struct psb_gem_object by acquiring
the GEM object's reservation lock; as it's supposed to be. The
use of the GTT mutex can now be moved into GTT code.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 12
1 f
Acquire the GTT mutex in psb_gtt_{insert,remove}_pages(). Remove
locking from callers. Also remove the GTT locking around the resume
code. Resume does not run concurrently with other GTT operations.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 1
Move the setup code for GTT/GATT memory ranges into a new helper and
call the function from psb_gtt_init() and psb_gtt_resume(). Removes
code duplication.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/gtt.c | 153 +++
1 file changed, 64 insertions(+)
The semaphore at struct psb_mmu_driver.sem protects access to the MMU
fields. Additional locking with struct psb_gtt.sem is unnecessary. Remove
the field and related code.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 7 ---
drivers/gpu/d
The GTT init, fini and resume functions contain both, GTT and GEM,
code. Split each into a separate GTT and a GEM function. The GEM
code is responsible for mmap_mutex and the stolen memory area. The
rest of the functionality is left in GTT functions.
Signed-off-by: Thomas Zimmermann
Acked-by: Pat
Inline psb_gtt_restore() into its only caller in power.c.
Perform the GTT restoration in psb_gem_mm_resume(). The restoration
step is part of GEM anyway and will be moved over at some point.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 15 ++-
Calculate the number of pages in the BO's backing storage from
the size. Remove the npage field.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 9 +
drivers/gpu/drm/gma500/gem.h | 1 -
drivers/gpu/drm/gma500/gma_display.c |
Move the code for enabling and disabling the GTT into helpers and call
the functions in psb_gtt_init(), psb_gtt_fini() and psb_gtt_resume().
Removes code duplication.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/gtt.c | 81
1 file changed, 46 i
Replace psb_gtt_takedown() with finalizer function that is only called
for unloading the driver. Use roll-back pattern for error handling in
psb_gtt_init() and _resume(). Also fixes a bug where vmap_addr was never
unmapped.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers
Move GEM functions from gtt.c to gem.c. Adapt some names. No
functional changes.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 133 +++
drivers/gpu/drm/gma500/gem.h | 12 +++
drivers/gpu/drm/gma500/gtt.c |
The current implementation of psb_gtt_init() also does resume
handling. Move the resume code into its own helper.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 122 ++-
drivers/gpu/drm/gma500/gtt.h | 2 +-
dr
The GTT init and restore functions contain logic to populate the
GTT entries. Move the code into helper functions.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 115 +--
1 file changed, 68 insertions(+), 47 deletio
Refactor and simplify various parts of the memory management. This
includes locking, initialization and finalizer functions, and code
organization.
Tested on Atom N2800 hardware.
v2:
* put common code in psb_gtt_{init,fini,resume}() into
helpers (Sam, Patrik)
Thomas Zimmermann
Hi Suraj
On 3/8/2022 6:30 AM, Kandpal, Suraj wrote:
Hi Abhinav,
Hi,
Hi,
Hi Abhinav,
Hi Laurent
Ok sure, I can take this up but I need to understand the proposal
a little bit more before proceeding on this. So we will discuss
this in another email where we specifically talk about the
connec
Hi
Am 08.03.22 um 13:07 schrieb Patrik Jakobsson:
On Tue, Mar 8, 2022 at 9:48 AM Thomas Zimmermann wrote:
Hi Sam and Patrik
Am 07.03.22 um 22:02 schrieb Patrik Jakobsson:
On Mon, Mar 7, 2022 at 8:07 PM Sam Ravnborg wrote:
Hi Thomas,
One comment below.
On Sun, Mar 06, 2022 at 09:36:15PM
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Implement struct drm_driver.dumb_create_fbdev with the helpers
> provided by GEM SHMEM. Fbdev deferred I/O will now work without
> an intermediate shadow buffer for mmap.
>
> As the virtio driver replaces several of the regular GEM SHMEM
> functions with
On Tue, Mar 1, 2022 at 6:14 PM Dmitry Baryshkov
wrote:
>
> Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix
> indentation for another brace, so it matches the corresponding line.
>
> Reported-by: Rob Herring
> Cc: Loic Poulain
> Reviewed-by: Bjorn Andersson
> Signed-off-by: D
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Implement struct drm_driver.dumb_create_fbdev for GEM SHMEM. The
> created buffer object returned by this function implements deferred
> I/O for its mmap operation.
>
> Add this feature to a number of drivers that use GEM SHMEM helpers
> as shadow planes
On 3/8/22 19:29, Rob Clark wrote:
> On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
> wrote:
>>
>> Hello,
>>
>> This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
>> During OOM, the shrinker will release BOs that are marked as "not needed"
>> by userspace using the new madvise
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd
Though the parade bridge chip is a little bit of a black box, I'm at
least interested in hearing about changes to the driver since this
bridge chip is used on some Chromebooks that I'm involved with.
Signed-off-by: Douglas Anderson
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
dif
I've spent quite a bit of time poking at this driver and it's used on
several Chromebooks I'm involved with. I'd like to get notified about
patches. Add myself as a reviewer. It's expected that changes will
still be landed through drm-misc as they always have been.
Signed-off-by: Douglas Anderson
The bindings for bridge chips should also get the same maintainers
entry so the right people get notified about bindings changes.
Signed-off-by: Douglas Anderson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0216d2ffe728..a73179d55d00 100644
On Tue, Mar 8, 2022 at 10:53 AM Fabio Estevam wrote:
>
> On Tue, Mar 8, 2022 at 3:48 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Avoid going down devfreq paths on devices where devfreq is not
> > initialized.
> >
> > v2: Change has_devfreq() logic [Dmitry]
> >
> > Reported-by: Linux Kern
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Add drm_fb_helper_vm_page_mkwrite(), a helper to track pages written
> by fbdev userspace. DRM drivers should use this function to implement
> fbdev deferred I/O.
>
> Signed-off-by: Thomas Zimmermann
> ---
Reviewed-by: Javier Martinez Canillas
--
Be
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [RFC 18/28] drm: rcar-du: Add RZ/G2L LCDC Support
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Wed, Jan 12, 2022 at 05:46:02PM +, Biju Das wrote:
> > The LCD controller is composed of Frame Compression Processor (FCPVD),
> > Video Sig
On Tue, Mar 8, 2022 at 3:48 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Avoid going down devfreq paths on devices where devfreq is not
> initialized.
>
> v2: Change has_devfreq() logic [Dmitry]
>
> Reported-by: Linux Kernel Functional Testing
> Reported-by: Anders Roxell
> Signed-off-by: Rob Cl
From: Rob Clark
Avoid going down devfreq paths on devices where devfreq is not
initialized.
v2: Change has_devfreq() logic [Dmitry]
Reported-by: Linux Kernel Functional Testing
Reported-by: Anders Roxell
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 +++
On Mon, Feb 28, 2022 at 09:29:52PM -0800, Matt Roper wrote:
Platforms with FlatCCS do not use auxiliary planes for compression
control data and thus do not need traditional aux table invalidation
(and the registers no longer even exist).
Original-author: CQ Tang
Signed-off-by: Matt Roper
---
dr
On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a warning
when wbinvd_on_all_cpus when its being used o
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Provide struct drm_driver.dumb_create_fbdev, a callback hook for
> fbdev dumb buffers. Wire up fbdev and client helpers to use the new
> interface, if present.
>
> This acknowledges the fact that fbdev buffers are different. The most
> significant differ
commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and
update functions") introduced a regression for g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.
MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
MGA1064_PI
On 08/03/2022 18:31, Greg KH wrote:
On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
setup into compute and update functions") introduced a regression for
g200wb and g200ew.
No need for all those digits in
On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
> commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
> setup into compute and update functions") introduced a regression for
> g200wb and g200ew.
No need for all those digits in the sha1, see below:
> The PLLs
On 3/3/22 21:58, Thomas Zimmermann wrote:
> DRM drivers will be able to handle deferred I/O by themselves. So
> a driver will be able to use deferred I/O without an intermediate
> shadow buffer.
>
> Prepare fbdev emulation by separating shadow buffers and deferred
> I/O from each other.
>
> Signe
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Refactor the page-write handler and export it as helper function
> fb_deferred_io_page_mkwrite(). Drivers that implement struct
> vm_operations_struct.page_mkwrite for deferred I/O should use the
> function to let fbdev track written pages of mmap'ed fram
commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
setup into compute and update functions") introduced a regression for
g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.
MGA1064_WB_PIX_PLLC_N/M/P was mistaken
On Tue, 8 Mar 2022 at 19:55, Vinod Polimera wrote:
>
> use max clock during probe/bind sequence from the opp table.
> The clock will be scaled down when framework sends an update.
>
> Signed-off-by: Vinod Polimera
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
> 1 file changed, 3 inser
On 08/03/2022 13:59, Arunpravin wrote:
On 07/03/22 10:11 pm, Matthew Auld wrote:
On 07/03/2022 14:37, Arunpravin wrote:
place BUG_ON(order < min_order) outside do..while
loop as it fails Unigine Heaven benchmark.
Unigine Heaven has buffer allocation requests for
example required pages are 16
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Changes in v2:
- Remove assigned-clock-rate pr
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: 08c2a076d1("arm64: dts: qcom: sdm845: A
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: a3db7ad1af("arm64: dts: qcom: sc7180: a
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: 7c1dffd471("arm64: dts: qcom: sm8250.dt
use max clock during probe/bind sequence from the opp table.
The clock will be scaled down when framework sends an update.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/d
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Changes in v2:
- Remove assigned-clock-rate pr
This patch is continuation of the effort to move all pointers in i915,
which at any point may be pointing to device memory or system memory, to
iosys_map interface.
More details about the need of this change is explained in the patch
series which initiated this task
https://patchwork.freedesktop.or
Hi Javier,
On Mon, Feb 14, 2022 at 2:37 PM Javier Martinez Canillas
wrote:
> This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
> OLED display controllers.
>
> It's only the core part of the driver and a bus specific driver is needed
> for each transport interface supported
On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
wrote:
>
> Hello,
>
> This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
> During OOM, the shrinker will release BOs that are marked as "not needed"
> by userspace using the new madvise IOCTL. The userspace in this case is
> the M
On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
> On 3/8/22 14:49, Maxime Ripard wrote:
> > On Tue, Mar 08, 2022 at 02:27:40PM +0100, Marek Vasut wrote:
> > > On 3/8/22 13:51, Maxime Ripard wrote:
> > > > On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wrote:
> > > > > On 3/8/22
Hi Javier,
On Mon, Feb 14, 2022 at 2:37 PM Javier Martinez Canillas
wrote:
> Add support to convert from XR24 to reversed monochrome for drivers that
> control monochromatic display panels, that only have 1 bit per pixel.
>
> The function does a line-by-line conversion doing an intermediate step
On Fri, Mar 4, 2022 at 5:49 PM Chun-Kuang Hu wrote:
>
> Hi, Rob:
>
> Would you like to take this series into your tree, or I take this
> series into my tree?
I can't. I don't have the broken commits in my tree.
Rob
From: Chen-Yu Tsai
Currently the ssd130x driver only sets the segment remap setting when
the device tree requests it; it however does not clear the setting if
it is not requested. This leads to the setting incorrectly persisting
if the hardware is always on and has no reset GPIO wired. This might
From: Chen-Yu Tsai
The SSD130x's command to toggle COM scan direction uses bit 3 and only
bit 3 to set the direction of the scanout. The driver has an incorrect
GENMASK(3, 2), causing the setting to be set on bit 2, rendering it
ineffective.
Fix the mask to only bit 3, so that the requested sett
On 3/8/22 16:17, Dmitry Osipenko wrote:
> @@ -246,20 +246,28 @@ static int virtio_gpu_plane_prepare_fb(struct drm_plane
> *plane,
> struct virtio_gpu_device *vgdev = dev->dev_private;
> struct virtio_gpu_framebuffer *vgfb;
> struct virtio_gpu_object *bo;
> + int err;
>
>
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