Hi Nikolaus,
On Wed, Nov 24, 2021 at 5:31 PM H. Nikolaus Schaller wrote:
> > Am 24.11.2021 um 17:21 schrieb Geert Uytterhoeven :
> > On Wed, Nov 24, 2021 at 5:19 PM H. Nikolaus Schaller
> > wrote:
> >>> Am 23.11.2021 um 21:10 schrieb Paul Cercueil :
> >>> Le mar., nov. 23 2021 at 19:13:59 +0100
Hi Arnd,
I love your patch! Perhaps something to improve:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on tiwai-sound/for-next staging/staging-testing
linus/master v5.16-rc2 next-20211125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And w
On 28/04/2021 22:36, Rob Clark wrote:
From: Rob Clark
Currently if userspace manages to fill up the ring faster than the GPU
can consume we (a) spin for up to 1sec, and then (b) overwrite the
ringbuffer contents from previous submits that the GPU is still busy
executing. Which predictably goes
On 04/05/2021 07:35, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2021-04-21 16:37:38)
Add checking aux read/write status at both dp_link_parse_sink_count()
and dp_link_parse_sink_status_filed() to avoid long timeout delay if
s/filed/field/
dp aux read/write failed at timeout due to cable unplu
Hi Andrej and all,
I'm trying to convert existing exynos dsi driver to bridge and make
them accessible for i.MX8MM platform.
I've a few questions on the existing exynos dsi driver and which is
indeed incompatible to proceed to make the bridge conversion.
1. Hotplug event
Commit from 295e7954c0d
Hi Laurent,
On Thu, Nov 25, 2021 at 3:53 AM Laurent Pinchart
wrote:
>
> Hi Jagan,
>
> Thank you for the patch.
>
> On Wed, Nov 24, 2021 at 10:55:52PM +0530, Jagan Teki wrote:
> > TI DLPC3433 is a MIPI DSI based display controller bridge
> > for processing high resolution DMD based projectors.
> >
Hi Fabio,
On Thu, Nov 25, 2021 at 12:47 AM Fabio Estevam wrote:
>
> Hi Jagan,
>
> On Wed, Nov 24, 2021 at 2:26 PM Jagan Teki wrote:
> >
> > TI DLPC3433 is a MIPI DSI based display controller bridge
> > for processing high resolution DMD based projectors.
> >
> > It has a flexible configuration o
Hi Igor,
just some nits on the commit message.
On Mon, Nov 22, 2021 at 04:43:52PM -0300, Igor Torrente wrote:
> The `drm_mode_config_init` was deprecated since c3b790e commit, and it's
When referring to other commits, it's best to write it as 'commit <12-digit-SHA>
("description")' [1]. Also, im
Am 2021-11-15 um 2:30 p.m. schrieb Alex Sierra:
> Device Coherent type uses device memory that is coherently accesible by
> the CPU. This could be shown as SP (special purpose) memory range
> at the BIOS-e820 memory enumeration. If no SP memory is supported in
> system, this could be faked by setti
Hi Jagan,
Thank you for the patch.
On Wed, Nov 24, 2021 at 10:55:52PM +0530, Jagan Teki wrote:
> TI DLPC3433 is a MIPI DSI based display controller bridge
> for processing high resolution DMD based projectors.
>
> It has a flexible configuration of MIPI DSI signal input
> produces RGB565, RGB666
On 11/24/21 9:07 AM, Noralf Trønnes wrote:
Hi,
This patchset adds a missing piece for decommissioning the
staging/fbtft/fb_st7735r.c driver namely a way to configure the
controller from Device Tree.
All fbtft drivers have builtin support for one display panel and all
other panels using that con
Hi Dave and Daniel,
Only one fix for this round. Sending earlier today due to Holiday in US
tomorrow.
Here goes drm-intel-fixes-2021-11-24:
Fix wakeref handling of PXP suspend.
Thanks,
Rodrigo.
The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6:
Linux 5.16-rc2 (2021
From: Rob Clark
If you don't realize is_a650_family() also encompasses a660 family,
you'd think that the debug buffer is double allocated. Add a comment
to make this more clear.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +++
1 file changed, 3 insertions(+)
diff -
From: Rob Clark
It appears to be a GMU fw build option whether it does anything with
debug and log buffers, but if they are all zeros it won't add anything
to the devcore size.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 12
1 file changed, 12 insert
From: Rob Clark
This also includes a history of start index of the last 8 messages on
each queue, since parsing backwards to decode recently sent HFI messages
is hard(ish).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 48 -
drivers/gpu/drm/msm/
From: Rob Clark
Turn it into a thing we can use to snapshot other GMU buffers.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 34 +
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/dri
From: Rob Clark
We don't expect either of these conditions to ever be true, so let's get
shouty if they are.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/ms
From: Rob Clark
Re-work the boost and idle clamping to use PM QoS requests instead, so
they get aggreggated with other requests (such as cooling device).
This does have the minor side-effect that devfreq sysfs min_freq/
max_freq files now reflect the boost and idle clamping, as they show
(despit
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 71e52b2b2025..e1774ea342b1 100644
-
From: Rob Clark
Looks like 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before
clamping freq") was badly rebased on top of efb8a170a367 ("drm/msm:
Fix devfreq NULL pointer dereference on a3xx") and ended up with
the NULL check in the wrong place.
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms d
From: Rob Clark
This was supposed to be a relative timer, not absolute.
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before clamping freq")
Signed-off-by: Rob Clark
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
From: Akhil P Oommen
Capture gmu log in coredump to enhance debugging.
Signed-off-by: Akhil P Oommen
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.
From: Rob Clark
This adds additional snapshotting for interesting GMU buffers to the
devcore dumps, adds a couple WARN_ON()s, etc. (Plus a bonus comment)
Akhil P Oommen (1):
drm/msm/a6xx: Capture gmu log in devcoredump
Rob Clark (6):
drm/msm/gpu: Name GMU bos
drm/msm/gpu: Add some WARN_O
After getting the regmap size from the device tree we should
reduce the ranges to the really available registers. This
allows to read only existing registers from the debug fs
and makes the regmap check out-of-bounds access.
For the jz4780 we have done this already.
Suggested-for: Paul Cercueil
From: Paul Boddie
We need to hook up
* HDMI connector
* HDMI power regulator
* JZ4780_CLK_HDMI @ 27 MHz
* DDC pinmux
* HDMI and LCDC endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 72 -
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add Kconfig DRM_INGENIC_DW_HDMI, Makefile and driver code.
Signed-off-by: Paul Boddie
Signed-off-by:
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H.
Enable CONFIG options as modules.
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/configs/ci20_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index ab7ebb0668340..cc69b21585
This changes the way the regmap is allocated to prepare for the
later addition of the JZ4780 which has more registers and bits
than the others.
Therefore we make the regmap as big as the reg property in
the device tree tells.
Suggested-by: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add jz4780 device tree setup.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
a
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
We also add generic ddc-i2c-bus to synopsys,dw-hdmi.yaml
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger
PATCH V9 2021-11-24 22:29:14:
- patch 6/8: remove optional <0> for assigned-clocks and unintentionally
included "unwedge" setup (found by p...@crapouillou.net)
- patch 4/8: some cosmetics
make regulator enable/disable only if not NULL (found by
p...@crapouillou.net)
simp
Hi Paul,
>>> You probably should disable the regulator (if not NULL) here.
>> Indeed. Would it be ok to make struct regulator *regulator static
>> or do we need dynamically allocated memory?
>
> static non-const is almost always a bad idea, so avoid it.
Well some years ago it was a perfectly si
Hi Dave, Daniel,
Fixes for 5.16.
The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6:
Linux 5.16-rc2 (2021-11-21 13:47:39 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.16-2021-11-24
for you to fe
On 16/11/2021 09:22, Vinod Koul wrote:
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Signed-off-by: Vinod Koul
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi
le32_to_cpu() was put around the wrong operand in the descriptor magic
value check. Fix this and put it around the descriptor value which is the
one that is in little endian format.
Fixes: 40e1a70 ("drm: Add GUD USB Display driver")
Reported-by: kernel test robot
Signed-off-by: Noralf Trønnes
--
On 15/11/2021 21:48, Kuogee Hsieh wrote:
Currently the msm_dp_*** functions implement the same sequence which would
happen when drm_bridge is used. hence get rid of this intermediate layer
and align with the drm_bridge usage to avoid customized implementation.
Signed-off-by: Kuogee Hsieh
Chang
On 2021-11-24 5:20 a.m., Jiapeng Chong wrote:
Fix the following coccicheck warning:
./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING
comparing pointer to 0.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fp
Hi Jagan,
On Wed, Nov 24, 2021 at 2:26 PM Jagan Teki wrote:
>
> TI DLPC3433 is a MIPI DSI based display controller bridge
> for processing high resolution DMD based projectors.
>
> It has a flexible configuration of MIPI DSI signal input
> produces RGB565, RGB666, RGB888 output format with maximu
Upon failure, dma_alloc_coherent() returns NULL. If that does happen,
passing some uninitialised stack contents to dma_mapping_error() - which
belongs to a different API in the first place - has precious little
chance of detecting it.
Also include the correct header, because the fragile transitive
On Tue, 2021-11-23 at 16:18 +0100, Robert Foss wrote:
> Hey Martyn,
>
> On Tue, 16 Nov 2021 at 13:28, Martyn Welch
> wrote:
> >
> > In the configuration used by the b850v3, the STDP2690 is used to read
> > EDID
> > data whilst it's the STDP4028 which can detect when monitors are
> > connected.
>
Hi Nikolaus,
Le mer., nov. 24 2021 at 17:13:30 +0100, H. Nikolaus Schaller
a écrit :
Am 23.11.2021 um 21:05 schrieb Paul Cercueil :
Hi Nikolaus,
I keep seeing a few things, sorry.
no problem.
Le mar., nov. 23 2021 at 19:13:57 +0100, H. Nikolaus Schaller
a écrit :
From: Paul
23.11.2021 01:21, Arnd Bergmann пишет:
> From: Arnd Bergmann
>
> The DMA resource is never set up anywhere, and passing this as slave_id
> has not been the proper procedure in a long time.
>
> As a preparation for removing all slave_id references from the ALSA code,
> remove this one.
>
> Accor
24.11.2021 19:47, Arnd Bergmann пишет:
> On Wed, Nov 24, 2021 at 5:32 PM Dmitry Osipenko wrote:
>> 23.11.2021 01:21, Arnd Bergmann пишет:
>>
>> The commit message is correct, however you could remove even more code
>> here. But there is no need to make a v3 just because this patch because
>> I alr
24.11.2021 19:40, Akhil R пишет:
>> 24.11.2021 10:18, Akhil R пишет:
*i2c_dev)
> i2c_dev->is_vi = true; }
How are you going to differentiate the VI I2C from a non-VI? This
doesn't look right.
>>> This patch adds the ACPI support to only non-VI I2C. The device_ids i
TI DLPC3433 is a MIPI DSI based display controller bridge
for processing high resolution DMD based projectors.
It has a flexible configuration of MIPI DSI signal input
produces RGB565, RGB666, RGB888 output format with maximum
of 720p resolution.
Add bridge driver for it.
Signed-off-by: Christop
TI DLPC3433 is a MIPI DSI based display controller bridge
for processing high resolution DMD based projectors.
It has a flexible configuration of MIPI DSI signal input
produces RGB565, RGB666, RGB888 output format with maximum
of 720p resolution in 60 and 120 Hz refresh rates.
Add dt-bingings for
On 16/11/2021 09:22, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Nit: I think patch description is a bit inaccurate, since we pass DSC
parameters from panel to DSI host rather
Hi Paul,
> Am 23.11.2021 um 21:44 schrieb H. Nikolaus Schaller :
>
> Hi Paul,
>
>> Am 23.11.2021 um 21:12 schrieb Paul Cercueil :
>>
>> Hi Nikolaus,
>>
>> I think if you can fix the last few things I commented on, and I get an ACK
>> from Rob for the Device Tree related patches, then it will
On Wed, Nov 24, 2021 at 5:32 PM Dmitry Osipenko wrote:
> 23.11.2021 01:21, Arnd Bergmann пишет:
>
> The commit message is correct, however you could remove even more code
> here. But there is no need to make a v3 just because this patch because
> I already prepared patchset that revives this S/PDI
> 24.11.2021 10:18, Akhil R пишет:
> >> *i2c_dev)
> >>> i2c_dev->is_vi = true; }
> >> How are you going to differentiate the VI I2C from a non-VI? This
> >> doesn't look right.
> > This patch adds the ACPI support to only non-VI I2C. The device_ids in
> > match table are added accord
23.11.2021 01:21, Arnd Bergmann пишет:
> From: Arnd Bergmann
>
> The DMA resource is never set up anywhere, and passing this as slave_id
> has not been the proper procedure in a long time.
>
> As a preparation for removing all slave_id references from the ALSA code,
> remove this one.
>
> Accor
Hi Geert,
> Am 24.11.2021 um 17:21 schrieb Geert Uytterhoeven :
>
> Hi Nikolaus,
>
> On Wed, Nov 24, 2021 at 5:19 PM H. Nikolaus Schaller
> wrote:
>>> Am 23.11.2021 um 21:10 schrieb Paul Cercueil :
>>> Le mar., nov. 23 2021 at 19:13:59 +0100, H. Nikolaus Schaller
>>> a écrit :
+assi
On 16/11/2021 09:22, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 16 +++-
include/drm/drm_panel
On 24/11/2021 19:21, Dmitry Baryshkov wrote:
On 16/11/2021 09:22, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing informa
> Am 24.11.2021 um 03:59 schrieb Rob Herring :
>
> On Tue, 23 Nov 2021 19:13:56 +0100, H. Nikolaus Schaller wrote:
>> From: Sam Ravnborg
>>
>> Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
>> Based on .txt binding from Zubair Lutfullah Kakakhel
>>
>> We also add generic ddc
Hi Nikolaus,
On Wed, Nov 24, 2021 at 5:19 PM H. Nikolaus Schaller wrote:
> > Am 23.11.2021 um 21:10 schrieb Paul Cercueil :
> > Le mar., nov. 23 2021 at 19:13:59 +0100, H. Nikolaus Schaller
> > a écrit :
> >> +assigned-clock-rates = <4800>, <0>, <5400>, <0>, <2700>;
> >> };
> >>
On 16/11/2021 09:22, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-of
Hi Rob and Paul,
> Am 24.11.2021 um 10:17 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> Le mar., nov. 23 2021 at 19:13:56 +0100, H. Nikolaus Schaller
> a écrit :
>> From: Sam Ravnborg
>> Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
>> Based on .txt binding from Zubair Lutful
> Am 23.11.2021 um 21:10 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> Le mar., nov. 23 2021 at 19:13:59 +0100, H. Nikolaus Schaller
> a écrit :
>> From: Paul Boddie
>> We need to hook up
>> * HDMI connector
>> * HDMI power regulator
>> * JZ4780_CLK_HDMI @ 27 MHz
>> * DDC pinmux
>> * HDMI an
> Am 23.11.2021 um 21:05 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> I keep seeing a few things, sorry.
no problem.
>
>
> Le mar., nov. 23 2021 at 19:13:57 +0100, H. Nikolaus Schaller
> a écrit :
>> From: Paul Boddie
>> A specialisation of the generic Synopsys HDMI driver is employed f
24.11.2021 10:18, Akhil R пишет:
>> *i2c_dev)
>>> i2c_dev->is_vi = true;
>>> }
>> How are you going to differentiate the VI I2C from a non-VI? This doesn't
>> look
>> right.
> This patch adds the ACPI support to only non-VI I2C. The device_ids in match
> table
> are added according
On 16/11/2021 09:22, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 fi
On 16/11/2021 09:22, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compa
On 16/11/2021 09:22, Vinod Koul wrote:
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/
On Wed, 24 Nov 2021 at 18:40, Dmitry Baryshkov
wrote:
>
> On 16/11/2021 09:22, Vinod Koul wrote:
> > We cannot enable mode_3d when we are using the DSC. So pass
> > configuration to detect DSC is enabled and not enable mode_3d
> > when we are using DSC
> >
> > We add a helper dpu_encoder_helper_ge
On 16/11/2021 09:22, Vinod Koul wrote:
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_
On 16/11/2021 09:22, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off
On 16/11/2021 09:22, Vinod Koul wrote:
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
1 file chang
On 16/11/2021 09:22, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off
On 16/11/2021 09:22, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off
On 16/11/2021 09:22, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1
On 11/23/21 9:16 PM, Stephen Rothwell wrote:
Hi all,
Changes since 20211123:
on i386:
ld: drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.o: in function
`dscc_compute_dsc_parameters':
rc_calc_dpi.c:(.text+0x31f): undefined reference to `__udivdi3'
--
~Randy
On 18.10.2021 23:13, Andrzej Hajda wrote:
> Beside updating email, the patch updates maintainers
> of Samsung drivers.
>
> Signed-off-by: Andrzej Hajda
> ---
> .mailmap| 1 +
> MAINTAINERS | 13 -
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/.mailmap b/.m
On Wed, Nov 24, 2021 at 08:55:39AM -0500, Rodrigo Vivi wrote:
> On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
> >
> > On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > > >
> > > > On 17/11/2021 22:49, Vinay Belgaum
Add support for initializing the controller from device properties when
the compatible is "sitronix,st7735r".
The rotation property does not apply in this case since a matching
ADDRESS_MODE/madctl value is necessary.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/tiny/st7735r.c | 87
Hi,
This patchset adds a missing piece for decommissioning the
staging/fbtft/fb_st7735r.c driver namely a way to configure the
controller from Device Tree.
All fbtft drivers have builtin support for one display panel and all
other panels using that controller are configured using the Device Tree
Add helper functions for configuring a MIPI DBI controller from device
properties.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/drm_mipi_dbi.c | 139 +
include/drm/drm_mipi_dbi.h | 3 +
2 files changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/dr
Add initialization properties that are commonly used to initialize the
controller for a specific display panel. It is common for displays to have
a datasheet listing the necessary controller settings or some example code
doing the same. These settings can be matched directly to the DT
properties.
The datasheet lists the minimum Serial clock cycle (Write) as 66ns which is
15MHz. Mostly it can do much better than that and is in fact often run at
32MHz. With a clever driver that runs configuration commands at a low speed
and only the pixel data at the maximum speed the configuration can't be
m
There are other ways than using a gpio to reset the controller so make
this property optional.
Signed-off-by: Noralf Trønnes
---
Documentation/devicetree/bindings/display/sitronix,st7735r.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sitronix,s
The backlight property was lost during conversion to yaml in commit
abdd9e3705c8 ("dt-bindings: display: sitronix,st7735r: Convert to DT schema").
Put it back.
Fixes: abdd9e3705c8 ("dt-bindings: display: sitronix,st7735r: Convert to DT
schema")
Signed-off-by: Noralf Trønnes
---
Documentation/de
----
> >>> 1380.decon not bound
> >>> 1388.decon not bound
> >>> 1393.micnot bound
> >>> (unknown)
; 1380.decon not bound
>>> 1388.decon not bound
>>> 1393.mic not bound
>>> (unknown) not registered
>>>
This code accidentally returns IS_ERR(), which is 1, instead of
propagating the negative error code. The caller doesn't check for
errors so it doesn't affect run time at all.
Fixes: 566fef1226c1 ("drm/bridge: anx7625: add HDMI audio function")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/br
The "offset" is a u32 that comes from the user. The bug is that the
"offset + bytes" operation can have an integer overflow problem which
leads to an out of bounds access.
Fixes: 4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space
virtualization")
Signed-off-by: Dan Carpenter
---
drivers
Hi Chunfeng,
Quoting Chunfeng Yun (2021-11-13 08:48:37)
> On Wed, 2021-11-10 at 14:06 +0100, Guillaume Ranquet wrote:
> > From: Markus Schneider-Pargmann
> >
> > This is a new driver that supports the integrated DisplayPort phy for
> > mediatek SoCs, especially the mt8195. The phy is integrated i
On 2021-11-23 14:10, Robin Murphy wrote:
Host1x seems to be relying on picking up dma-mapping.h transitively from
iova.h, which has no reason to include it in the first place. Fix the
former issue before we totally break things by fixing the latter one.
CC: Thierry Reding
CC: Mikko Perttunen
C
On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
>
> On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > >
> > > On 17/11/2021 22:49, Vinay Belgaumkar wrote:
> > > > From: Chris Wilson
> > > >
> > > > Everytime we come
Hi,
Thanks for all your input, really appreciated.
Quoting Maxime Ripard (2021-11-16 15:51:12)
> Hi,
>
> On Mon, Nov 15, 2021 at 09:33:52AM -0500, Guillaume Ranquet wrote:
> > Quoting Maxime Ripard (2021-11-15 11:11:29)
> > > > The driver creates a child device for the phy. The child device will
>
On Wed, Nov 24, 2021 at 10:44:09AM +0100, Jan Kara wrote:
> On Tue 23-11-21 12:24:20, Luis Chamberlain wrote:
> > From: Xiaoming Ni
> >
> > There is no need to user boiler plate code to specify a set of base
> > directories we're going to stuff sysctls under. Simplify this by using
> > register_s
On Wed, Nov 24, 2021 at 12:53 AM Srinivas Pandruvada
wrote:
>
> On Tue, 2021-11-23 at 14:19 +0100, Rafael J. Wysocki wrote:
> > On Wed, Aug 18, 2021 at 8:08 AM Kees Cook
> > wrote:
> > >
> > > In preparation for FORTIFY_SOURCE performing compile-time and run-
> > > time
> > > field bounds checkin
https://bugzilla.kernel.org/show_bug.cgi?id=211807
Chatty (m...@chatty.de) changed:
What|Removed |Added
CC||m...@chatty.de
--- Comment #17
From: Anand K Mistry
commit 8244a3bc27b3efd057da154b8d7e414670d5044f upstream.
drm_gem_ttm_mmap() drops a reference to the gem object on success. If
the gem object's refcount == 1 on entry to drm_gem_prime_mmap(), that
drop will free the gem object, and the subsequent drm_gem_object_get()
will b
From: Thomas Zimmermann
commit 995f54ea962e03ec08b8bc6a4fe11a32b420edd3 upstream.
The GEM CMA helpers allocate non-coherent (i.e., cached) backing storage
with dma_alloc_noncoherent(), but release it with dma_free_wc(). Fix this
with a call to dma_free_noncoherent(). Writecombining storage is st
Instead of calling the debug operation directly.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9be5
We have the BO pointer in the base structure now as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 49 -
1 file changed, 18 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/
This is provided by TTM now.
Also switch man->size to bytes instead of pages and fix the double
printing of size and usage in debugfs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/a
Keep track for which BO a resource was allocated.
This is necessary to move the LRU handling into the resources.
A bit problematic is i915 since it tries to use the resource
interface without a BO which is illegal from the conceptional
point of view.
v2: Document that this is a weak reference and
This is provided by TTM now.
Also switch man->size to bytes instead of pages and fix the double
printing of size and usage in debugfs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 50 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 +--
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