On 12.10.2021 00:13, Andrzej Hajda wrote:
On 08.10.2021 19:33, Dave Stevenson wrote:
On Thu, 7 Oct 2021 at 21:19, Andrzej Hajda
wrote:
On 07.10.2021 13:07, Dave Stevenson wrote:
On Tue, 5 Oct 2021 at 22:03, Andrzej Hajda
wrote:
On 05.10.2021 17:32, Dave Stevenson wrote:
Hi Andrzej
Thank
On Mon, Oct 11, 2021 at 10:24:29PM +0200, Lukas Wunner wrote:
> On Mon, Oct 11, 2021 at 09:06:07PM +0200, Nirmoy Das wrote:
> > Debugfs APIs returns encoded error on failure so use
> > debugfs_lookup() instead of checking for NULL.
> [...]
> > --- a/drivers/gpu/vga/vga_switcheroo.c
> > +++ b/driver
VCC needs to be enabled before releasing the enable GPIO.
Reviewed-by: Sam Ravnborg
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
b/drivers/gpu/d
The enable signal may not be controllable by the kernel. Make it
optional.
This is a similar to commit bbda1704fc15 ("drm/bridge: ti-sn65dsi86: Make
enable GPIO optional")
Reviewed-by: Laurent Pinchart
Reviewed-by: Sam Ravnborg
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/ti-sn65d
Changes in V2 of this set:
* Add patch from Laurent for fixing the binding regarding optional GPIO
* Reorder patches so bindings are changed beforehand
* Add small fixes from Sam's review
Alexander Stein (3):
drm/bridge: ti-sn65dsi83: Make enable GPIO optional
dt-bindings: drm/bridge: ti-sn65d
Add a VCC regulator which needs to be enabled before the EN pin is
released.
Reviewed-by: Sam Ravnborg
Signed-off-by: Alexander Stein
---
.../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/displ
From: Laurent Pinchart
The SN65DSI8x EN signal may be tied to VCC, or otherwise controlled by
means not available to the kernel. Make the GPIO optional.
Signed-off-by: Laurent Pinchart
Signed-off-by: Alexander Stein
---
.../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 1 -
1
Hi Sam,
On Mon, 11 Oct 2021 22:29:30 +0200, Sam Ravnborg wrote:
> > VCC needs to be enabled before releasing the enable GPIO.
> >
> > Signed-off-by: Alexander Stein
> > ---
> > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++-
> > 1 file changed, 14 insertions(+), 1 deletion(-)
> >
>
Signed-off-by: docfate111
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 87daa78a32b8..17
Hello,
We belong to a student group, LKCAMP [1], which is focused on sharing kernel and
free software development knowledge and mentoring newcomers to become
contributors to these projects.
As part of our efforts, we'll be organizing a hackathon to convert the drm
selftests in drivers/gpu/drm/sel
On Mon, Oct 11, 2021 at 9:10 AM Ramalingam C wrote:
>
> Details of the new features getting added as part of DG2 enabling and their
> implicit impact on the uAPI.
>
> Signed-off-by: Ramalingam C
> cc: Daniel Vetter
> cc: Matthew Auld
> ---
> Documentation/gpu/rfc/i915_dg2.rst | 47
On Thu, Oct 7, 2021 at 8:10 AM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Now that SCM can be a loadable module, we have to add another
> dependency to avoid link failures when ipa or adreno-gpu are
> built-in:
>
> aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe':
> ipa
On Wed 06 Oct 10:59 CDT 2021, Kuogee Hsieh wrote:
> Combo phy support both USB3 and DP simultaneously. USB3 is the
> master of combo phy so that USB3 should initialize and power on
> its phy before DP initialize its phy. At current implementation,
> DP driver initialize its phy happen earlier than
'inst' [-Werror=unused-variable]
491 | u32 inst, aper;
| ^~~~
cc1: all warnings being treated as errors
Caused by commit
404046cf4805 ("drm/nouveau/mmu/gp100-: drop unneeded assignment in the if
condition.")
I have used the drm-misc tree from next-20211011 for t
On 12/10/2021 02:41, Jessica Zhang wrote:
Add CRC support to DPU, which is currently not supported by
this driver. Only supports CRC for CRTC for now, but will extend support
to other blocks later on.
Tested on Qualcomm RB3 (debian, sdm845)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ms
On Tue, Oct 12, 2021 at 2:07 AM Kim Phillips wrote:
>
> Hi,
>
> On 10/5/21 1:10 PM, Kim Phillips wrote:
> > Hi, I occasionally see the below trace with Linus' master on an
> > AMD Milan system:
> >
> > [ 25.657322] BUG: kernel NULL pointer dereference, address:
> >
> > [ 25.6
On Mon, Oct 11, 2021 at 11:46:19AM +0200, Markus Schneider-Pargmann wrote:
> This controller is present on several mediatek hardware. Currently
> mt8195 and mt8395 have this controller without a functional difference,
> so only one compatible field is added.
>
> The controller can have two forms,
Enric Balletbo Serra 於 2021年10月8日 週五 下午9:33寫道：
>
> Hi Chun-Kuang,
>
> Thank you to take time to send this, for full series
>
> Tested-by: Enric Balletbo i Serra
>
> Display is now working again.
Applied to mediatek-drm-fixes [1].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu
Hi Markus,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next linus/master v5.15-rc5 next-20211011]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
The hangcheck selftest blocks per engine resets by setting magic bits in
the reset flags. This is incorrect for GuC submission because if the GuC
fails to reset an engine we would like to do a full GT reset. Do no set
these magic bits when using GuC submission.
Side note this lockless algorithm wi
On Mon, 11 Oct 2021 11:46:18 +0200, Markus Schneider-Pargmann wrote:
> DP_INTF is a similar functional block to mediatek,dpi but is different
> in that it serves the DisplayPort controller on mediatek SoCs and uses
> different clocks. Therefore this patch creates a new binding file for
> this funct
On Sun, Oct 10, 2021 at 10:42:45AM +0200, David Heidelberg wrote:
> Conversion of text binding for Adreno GPU to the YAML format.
Blank line needed.
> Signed-off-by: David Heidelberg
> ---
> v2:
> - added compatbile description from Rob Clark
> - dropped reg description
> - reg numbers inc
Add CRC support to DPU, which is currently not supported by
this driver. Only supports CRC for CRTC for now, but will extend support
to other blocks later on.
Tested on Qualcomm RB3 (debian, sdm845)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 169 +
On 10/4/2021 15:06, Matthew Brost wrote:
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between to parent and child is needed. This is implemented via custom
between to parent -> between parent
emit_bb_
On Sun, Oct 10, 2021 at 09:55:49AM +0300, Gal Pressman wrote:
> On 07/10/2021 14:40, Jason Gunthorpe wrote:
> > On Thu, Oct 07, 2021 at 01:43:00PM +0300, Gal Pressman wrote:
> >
> >> @@ -1491,26 +1493,29 @@ static int efa_create_pbl(struct efa_dev *dev,
> >>return 0;
> >> }
> >>
> >> -struc
On Mon, Oct 11, 2021 at 03:09:43PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> >
> > IGT: https://patchwork.freedesktop.org/patch
On 10/4/2021 3:06 PM, Matthew Brost wrote:
Parallel submission create composite fences (dma_fence_array) for excl /
shared slots in objects. The I915_GEM_BUSY IOCTL checks these slots to
determine the busyness of the object. Prior to patch it only check if
the fence in the slot was a i915_reque
On 08.10.2021 19:33, Dave Stevenson wrote:
On Thu, 7 Oct 2021 at 21:19, Andrzej Hajda wrote:
On 07.10.2021 13:07, Dave Stevenson wrote:
On Tue, 5 Oct 2021 at 22:03, Andrzej Hajda wrote:
On 05.10.2021 17:32, Dave Stevenson wrote:
Hi Andrzej
Thanks for joining in the discussion.
On Tue, 5
On 10/4/2021 15:06, Matthew Brost wrote:
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pu
Hi Markus,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next linus/master v5.15-rc5 next-20211011]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
hence the panel settings that were retrieved with a FEX dump are named
after the device NOT the actual panel.
The LCD in question is a 50 pin MISO TFT LCD panel of the resolution
1024x600 used by the aforementioned device.
Vers
Hi Markus,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next linus/master v5.15-rc5 next-20211011]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
On 2021-10-11 13:16, Marijn Suijten wrote:
div_u64_rem provides the result of the division and additionally the
remainder; don't use this function to solely calculate the remainder
while calculating the division again with div_u64.
A similar improvement was applied earlier to the 10nm pll in
5c1
Hi Guido,
Thank you for the patch.
On Mon, Oct 11, 2021 at 03:41:26PM +0200, Guido Günther wrote:
> media-bus-formats.h has them in hexadecimal as well so matching with
> that file saves one conversion when debugging.
>
> Signed-off-by: Guido Günther
> Reviewed-by: Lucas Stach
> Reviewed-by: R
On Mon, Oct 11, 2021 at 8:43 AM Michael Trimarchi
wrote:
>
> Hi
>
> On Sun, Jul 04, 2021 at 07:33:09PM +0530, Jagan Teki wrote:
> > Finding panel_or_bridge might vary based on associated
> > DSI devices like DSI panel, bridge, and I2C based DSI
> > bridge.
> >
> > 1. DSI panels and bridges will in
Hello,
On Mon, Oct 11, 2021 at 03:27:41PM +0200, Uwe Kleine-König wrote:
> this series is part of my new quest to make spi remove callbacks return
> void. Today they return an int, but the only result of returning a
> non-zero value is a warning message. So it's a bad idea to return an
> error cod
Hi Alexander,
On Wed, Oct 06, 2021 at 09:47:13AM +0200, Alexander Stein wrote:
> The enable signal may not be controllable by the kernel. Make it
> optional.
> This is a similar to commit bbda1704fc15 ("drm/bridge: ti-sn65dsi86: Make
> enable GPIO optional")
>
> Signed-off-by: Alexander Stein
Lo
On Wed, Oct 06, 2021 at 09:47:12AM +0200, Alexander Stein wrote:
> Add a VCC regulator which needs to be enabled before the EN pin is
> released.
>
> Signed-off-by: Alexander Stein
Looks good,
Reviewed-by: Sam Ravnborg
When you resend please put bindings patches first, we should not commit
cod
On Mon, Oct 11, 2021 at 09:06:07PM +0200, Nirmoy Das wrote:
> Debugfs APIs returns encoded error on failure so use
> debugfs_lookup() instead of checking for NULL.
[...]
> --- a/drivers/gpu/vga/vga_switcheroo.c
> +++ b/drivers/gpu/vga/vga_switcheroo.c
> @@ -914,7 +914,7 @@ static void vga_switchero
Hi Alexander,
On Wed, Oct 06, 2021 at 09:47:11AM +0200, Alexander Stein wrote:
> VCC needs to be enabled before releasing the enable GPIO.
>
> Signed-off-by: Alexander Stein
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
div_u64_rem provides the result of the division and additionally the
remainder; don't use this function to solely calculate the remainder
while calculating the division again with div_u64.
A similar improvement was applied earlier to the 10nm pll in
5c191fef4ce2 ("drm/msm/dsi_pll_10nm: Fix dividi
Hi Alexander,
On Wed, Oct 06, 2021 at 09:47:11AM +0200, Alexander Stein wrote:
> VCC needs to be enabled before releasing the enable GPIO.
>
> Signed-off-by: Alexander Stein
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
>
div_u64_rem provides the result of the division and additionally the
remainder; don't use this function to solely calculate the remainder
while calculating the division again with div_u64.
A similar improvement was applied earlier to the 10nm pll in
5c191fef4ce2 ("drm/msm/dsi_pll_10nm: Fix dividin
Hi AngeloGioacchino,
On Wed, Oct 06, 2021 at 03:51:50PM +0200, AngeloGioacchino Del Regno wrote:
> Convert the Toshiba TC358764 txt documentation to YAML.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
Thanks for all these conversions to DT-schema.
It would be very good if the changelog coul
On Mon, Oct 11, 2021 at 12:41:19PM +0100, Tvrtko Ursulin wrote:
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to th
Hi Randy,
On Sun, Oct 10, 2021 at 03:44:59PM -0700, Randy Dunlap wrote:
> Clean up all of the kernel-doc issues in drm_connector.c:
>
> drivers/gpu/drm/drm_connector.c:2611: warning: Excess function parameter
> 'connector' description in 'drm_connector_oob_hotplug_event'
> drivers/gpu/drm/drm_co
The hangcheck selftest blows on DG1 CI and aborts the BAT run.
Investigation is underway to root cause the failure but in the meantime
disable to this test on DG1 to unblock CI.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8
1 file changed, 8 insertio
Debugfs APIs returns encoded error on failure so use
debugfs_lookup() instead of checking for NULL.
CC: Lukas Wunner
CC: David Airlie
CC: Daniel Vetter
CC: Maarten Lankhorst
CC: Maxime Ripard
CC: Thomas Zimmermann
Signed-off-by: Nirmoy Das
---
drivers/gpu/vga/vga_switcheroo.c | 2 +-
1 fi
Do not check for NULL value as drm.primary->debugfs_root
will either contain a valid pointer or an encoded error
instead of NULL.
CC: Jani Nikula
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/debugfs_gt.c | 3 -
For debugfs directory, it is recommended to save the result
and pass over to next debugfs API for creating debugfs
files/directories. Error conditions are handled by debugfs APIs.
CC: Christian Koenig
CC: Huang Rui
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu
Debugfs APIs returns encoded error on failure instead of NULL
and for drm primary/minor debugfs directories, we save the
returned value in the dentry pointer and pass it on to drm
drivers to further create debugfs files/directories. Error
conditions are handled by debugfs APIs, so no need to check
On Mon, 11 Oct 2021, Greg KH wrote:
> On Mon, Oct 11, 2021 at 07:38:22PM +0300, Jani Nikula wrote:
>> On Mon, 11 Oct 2021, Greg KH wrote:
>> > On Mon, Oct 11, 2021 at 04:19:58PM +0200, Christian König wrote:
>> >> > > > > And then throw it away, later, when you want to remove the
>> >> > > > > d
On Mon, Oct 11, 2021 at 8:43 AM Markus Schneider-Pargmann
wrote:
>
> Hi,
>
> On Mon, Oct 11, 2021 at 08:36:18AM -0500, Rob Herring wrote:
> > On Mon, 11 Oct 2021 11:46:18 +0200, Markus Schneider-Pargmann wrote:
> > > DP_INTF is a similar functional block to mediatek,dpi but is different
> > > in t
On Mon, Oct 11, 2021 at 08:51:04PM +0530, Thanneeru Srinivasulu wrote:
> Replace DRM_ERROR with i915_probe_error to report early HuC failures.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
> 1 file changed, 2 inser
On Mon, Oct 11, 2021 at 08:51:03PM +0530, Thanneeru Srinivasulu wrote:
> Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++--
> 1 file changed, 2 inse
On Mon, Oct 11, 2021 at 08:51:05PM +0530, Thanneeru Srinivasulu wrote:
> Injecting probe errors -ENXIO for MMIO send.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On Mon, Oct 11, 2021 at 08:51:06PM +0530, Thanneeru Srinivasulu wrote:
> Inject probe errors -ENXIO, -EBUSY for CT send.
>
> Signed-off-by: Thanneeru Srinivasulu
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i9
perf_parallel_engines is micro benchmark to test i915 request
scheduling. The test creates a thread per physical engine and submits
NOP requests and waits the requests to complete in a loop. In execlists
mode this works perfectly fine as powerful CPU has enough cores to feed
each engine and process
On Mon 11 Oct 08:24 PDT 2021, khs...@codeaurora.org wrote:
> On 2021-10-08 09:44, Bjorn Andersson wrote:
> > On Fri 08 Oct 09:07 PDT 2021, khs...@codeaurora.org wrote:
> >
> > > On 2021-10-07 15:34, Stephen Boyd wrote:
> > > > Quoting khs...@codeaurora.org (2021-10-07 13:28:12)
> > > > > On 2021-
> -Original Message-
> From: C, Ramalingam
> Sent: Monday, October 11, 2021 9:12 AM
> To: dri-devel ; intel-gfx g...@lists.freedesktop.org>
> Cc: Daniel Vetter ; Auld, Matthew
> ; Tang, CQ ; Hellstrom,
> Thomas ; C, Ramalingam
> ; Daniel Vetter
> Subject: [PATCH 14/14] Doc/gpu/rfc/i91
On Mon, Oct 11, 2021 at 07:38:22PM +0300, Jani Nikula wrote:
> On Mon, 11 Oct 2021, Greg KH wrote:
> > On Mon, Oct 11, 2021 at 04:19:58PM +0200, Christian König wrote:
> >> > > > > And then throw it away, later, when you want to remove the
> >> > > > > directory,
> >> > > > > look it up with a ca
On 10/7/21 13:01, Marco Elver wrote:
> On Thu, Oct 07, 2021 at 11:58AM +0200, Vlastimil Babka wrote:
> [...]
>> - Add a CONFIG_STACKDEPOT_ALWAYS_INIT flag to keep using the current
>> well-defined point of allocation as part of mem_init(). Make CONFIG_KASAN
>> select this flag.
>> - Other user
On Mon, Oct 11, 2021 at 01:00:06AM -0700, Randy Dunlap wrote:
> Fix a build error on CONFIG_UML, which does not support (provide)
> wbinvd(). UML can use the generic mb() instead.
>
> ../drivers/gpu/drm/r128/ati_pcigart.c: In function ‘drm_ati_pcigart_init’:
> ../drivers/gpu/drm/r128/ati_pcigart.c
Hi Guido,
On Mon, Oct 11, 2021 at 03:41:22PM +0200, Guido Günther wrote:
> commit b776b0f00f24 ("drm: mxsfb: Use bus_format from the nearest bridge if
> present") added bus format probing to mxsfb this exposed several issues in the
> display stack as used on the Librem 5:
>
> The nwl bridge and t
Hi Uwe,
On Mon, Oct 11, 2021 at 03:27:42PM +0200, Uwe Kleine-König wrote:
> Up to now s6e63m0_remove() returns zero unconditionally. Make it return
> void instead which makes it easier to see in the callers that there is
> no error to handle.
>
> Also the return value of spi remove callbacks is i
On Mon, 11 Oct 2021, Greg KH wrote:
> On Mon, Oct 11, 2021 at 04:19:58PM +0200, Christian König wrote:
>> > > > > And then throw it away, later, when you want to remove the directory,
>> > > > > look it up with a call to debugfs_lookup() and pass that to
>> > > > > debugfs_remove() (which does so
On 10/11/21 6:26 PM, Sam Ravnborg wrote:
Hi Marek,
On Mon, Oct 11, 2021 at 01:21:33PM +0200, Marek Vasut wrote:
Add helper function to convert DT "data-mapping" property string value
into media bus format value, and deduplicate the code in panel-lvds.c
and lvds-codec.c .
Signed-off-by: Marek Va
Hi Marek,
On Mon, Oct 11, 2021 at 01:21:33PM +0200, Marek Vasut wrote:
> Add helper function to convert DT "data-mapping" property string value
> into media bus format value, and deduplicate the code in panel-lvds.c
> and lvds-codec.c .
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
> Cc:
Hi Oleksij,
On Mon, Oct 11, 2021 at 11:01:48AM +0200, Oleksij Rempel wrote:
> On Sat, Oct 09, 2021 at 05:12:44PM +0200, Sam Ravnborg wrote:
> > Hi Oleksij, Robin,
> >
> > On Thu, Sep 30, 2021 at 12:05:00PM +0200, Oleksij Rempel wrote:
> > > Add compatible and timings for the Innolux G070Y2-T02 pan
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
---
Documentation/gpu/rfc/i915_dg2.rst | 47 ++
Documentation/gpu/rfc/index.rst| 3 ++
2 file
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
incl
From: Ayaz A Siddiqui
Gen12.5+ devices support Flat CCS which reserved a portion of the device
memory to store compression metadata, during the clearing of device memory
buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of
From: CQ Tang
Gen12+ devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by: Matth
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/selftests/i9
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ramalingam C
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gtt.c |
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer sup
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
From: Matthew Auld
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9 +++--
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i91
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/in
This series introduces the enabling patches for new flat ccs feature and
64k page support for i915 local memory, along with documentation on the
uAPI impact.
64k page support
On discrete platforms, starting from DG2, we have to contend with GTT
page size restrictions when dealing
Hi,
On 10/5/21 1:10 PM, Kim Phillips wrote:
Hi, I occasionally see the below trace with Linus' master on an
AMD Milan system:
[ 25.657322] BUG: kernel NULL pointer dereference, address:
[ 25.665097] #PF: supervisor instruction fetch in kernel mode
[ 25.671448] #PF: error_
Injecting probe errors for MMIO send, CT send to make
probe flow more robust.
Use i915_probe_error to report probe injection errors.
Thanneeru Srinivasulu (4):
drm/i915/huc: Use i915_probe_error to report early CTB failures
drm/i915/huc: Use i915_probe_error to report early HuC failures
drm
Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/i
On 2021-10-08 09:44, Bjorn Andersson wrote:
On Fri 08 Oct 09:07 PDT 2021, khs...@codeaurora.org wrote:
On 2021-10-07 15:34, Stephen Boyd wrote:
> Quoting khs...@codeaurora.org (2021-10-07 13:28:12)
> > On 2021-10-07 13:06, Bjorn Andersson wrote:
> > > On Thu 07 Oct 12:51 PDT 2021, khs...@codeau
Injecting probe errors -ENXIO for MMIO send.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8f8182bf7c11..490d66712afc 1
Inject probe errors -ENXIO, -EBUSY for CT send.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 83764db0fd6d
Replace DRM_ERROR with i915_probe_error to report early HuC failures.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel
On 10/11/2021 4:19 PM, Christian König wrote:
Am 08.10.21 um 17:11 schrieb Greg KH:
On Fri, Oct 08, 2021 at 04:22:06PM +0200, Christian König wrote:
Hi guys,
thanks Nirmoy for forwarding this, there is seriously something
wrong with
the AMD mail servers.
On 10/8/2021 1:07 PM, Greg KH wro
Turn on the shmem tt backend, and enable shrinking.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/driver
This should let us do an accelerated copy directly to the shmem pages
when temporarily moving lmem-only objects, where the i915-gem shrinker
can later kick in to swap out the pages, if needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i9
We currently just evict lmem objects to system memory when under memory
pressure. For this case we might lack the usual object mm.pages, which
effectively hides the pages from the i915-gem shrinker, until we
actually "attach" the TT to the object, or in the case of lmem-only
objects it just gets mi
Attempt to document shrink_pin and the other relevant interfaces that
interact with it, before we start messing with it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 24 +-
drivers/gpu/drm/i915/ge
For cached objects we can allocate our pages directly in shmem. This
should make it possible(in a later patch) to utilise the existing
i915-gem shrinker code for such objects. For now this is still disabled.
v2(Thomas):
- Add optional try_to_writeback hook for objects. Importantly we need
to
We already do this when mapping the pages.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 -
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt
From: Thomas Hellström
Break out some shmem backend utils for future reuse by the TTM backend:
shmem_alloc_st(), shmem_free_st() and __shmem_writeback() which we can
use to provide a shmem-backed TTM page pool for cached-only TTM
buffer objects.
Main functional change here is that we now compute
The comment here is no longer accurate, since the current shrinker code
requires a full ref before touching any objects. Also unset_pages()
should already do the required make_unshrinkable() for us, if needed,
which is also nicely balanced with set_pages().
Signed-off-by: Matthew Auld
Cc: Thomas
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