Creates plane alpha and blend mode properties attached to plane.
Signed-off-by: Lowry Li
---
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
b/drivers/gpu/drm/arm/display/komeda/
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Brian
>Starkey
>Sent: Thursday, March 21, 2019 5:31 PM
>To: Shankar, Uma
>Cc: Syrjala, Ville ; Liviu Dudau
>;
>intel-...@lists.freedesktop.org; emil.l.veli...@gmail.com; dri-
>de...@list
>-Original Message-
>From: Brian Starkey [mailto:brian.star...@arm.com]
>Sent: Thursday, March 21, 2019 5:12 PM
>To: Shankar, Uma
>Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>Lankhorst,
>Maarten ; Syrjala, Ville
>;
>Sharma, Shashank ; emil.l.veli...@gmail.com
>-Original Message-
>From: Brian Starkey [mailto:brian.star...@arm.com]
>Sent: Thursday, March 21, 2019 5:17 PM
>To: Shankar, Uma
>Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>Lankhorst,
>Maarten ; Syrjala, Ville
>;
>Sharma, Shashank ; emil.l.veli...@gmail.com
>-Original Message-
>From: Brian Starkey [mailto:brian.star...@arm.com]
>Sent: Thursday, March 21, 2019 4:47 PM
>To: Shankar, Uma
>Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>Lankhorst,
>Maarten ; Syrjala, Ville
>;
>Sharma, Shashank ; emil.l.veli...@gmail.com
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Brian
>Starkey
>Sent: Thursday, March 21, 2019 5:01 PM
>To: Shankar, Uma
>Cc: Syrjala, Ville ; Liviu Dudau
>;
>intel-...@lists.freedesktop.org; emil.l.veli...@gmail.com; dri-
>de...@list
On Thu, 28 Mar 2019 at 10:14, Sonal Santan wrote:
>
>
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Wednesday, March 27, 2019 7:12 AM
> > To: Sonal Santan
> > Cc: Daniel Vetter ; dri-devel@lists.freedesktop.org;
On Thu, 14 Mar 2019 at 17:56, Boris Brezillon
wrote:
>
> On Thu, 28 Feb 2019 15:49:06 +0100
> Daniel Vetter wrote:
>
> > We kzalloc.
> >
> > Cc: Keith Packard
> > Signed-off-by: Daniel Vetter
>
> Reviewed-by: Boris Brezillon
Reviewed-by: Dave Airlie
>
> > ---
> > drivers/gpu/drm/drm_auth.c
commit 2e1c9b2867656ff9a469d23e1dfe90cf77ec0c72
Author: Tejun Heo
Date: Fri Mar 8 12:43:30 2013 -0800
idr: remove WARN_ON_ONCE() on negative IDs
We used to WARN_ON if we hit a negative id, it appears we don't
anymore, so just update the commit msg to reflect that info on where
the code cam
Hi Linus,
Weekly fixes roundup, nothing two serious, some usb device regressions
are fixed, and i915 GVT has a bigger fix but otherwise not really much
happening here.
Thanks,
Dave.
core:
- fb bpp check regression fix
- release/unplug fix
- use after free fixes
i915:
- fix mmap range checks
- f
On Fri, 29 Mar 2019 at 03:44, Alex Deucher wrote:
>
> Hi Dave, Daniel,
>
> New stuff for 5.2:
32-bit arm build:
/home/airlied/devel/kernel/dim/src/drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:
In function ‘smu_v11_0_notify_memory_pool_location’:
/home/airlied/devel/kernel/dim/src/drivers/
On Fri, Mar 29, 2019 at 5:31 AM Eric Anholt wrote:
>
> Daniel Vetter writes:
>
> > On Thu, Mar 28, 2019 at 03:12:23PM +0100, Neil Armstrong wrote:
> >> On 27/03/2019 20:06, Eric Anholt wrote:
> >> > Neil Armstrong writes:
> >> >
> >> >> Hi,
> >> >>
> >> >> On 26/03/2019 21:40, Vasily Khoruzhick
On Fri, Mar 29, 2019 at 2:30 AM YueHaibing wrote:
>
> Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
>
> Signed-off-by: YueHaibing
> ---
> drivers/gpu/drm/omapdrm/dss/hdmi4_core.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
Acked-by: Matteo Croce
--
Matteo Croce
There is a problem when often dpms goes from off to on. pm idle is not
in sync and the problem occurs. Modify pm_runtime_put from
asynchronous to synchronous.
Signed-off-by: Hoegeun Kwon
---
drivers/gpu/drm/vc4/vc4_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
Add very trivial allocation and import test for dma-heaps.
TODO: Still needs improvements
Cc: Benjamin Gaignard
Cc: Sumit Semwal
Cc: Liam Mark
Cc: Pratik Patel
Cc: Brian Starkey
Cc: Vincent Donnefort
Cc: Sudipto Paul
Cc: Andrew F. Davis
Cc: Xu YiPing
Cc: "Chenfeng (puck)"
Cc: butao
Cc:
From: "Andrew F. Davis"
This dummy test driver lets us do some very basic testing of
importing dma-bufs.
It is based originally on TI's out of tree "DMA-BUF physical
address user-space exporter" originally by
Andrew F. Davis
Cc: Benjamin Gaignard
Cc: Sumit Semwal
Cc: Liam Mark
Cc: Pratik Pa
From: "Andrew F. Davis"
This framework allows a unified userspace interface for dma-buf
exporters, allowing userland to allocate specific types of memory
for use in dma-buf sharing.
Each heap is given its own device node, which a user can allocate
a dma-buf fd from using the DMA_HEAP_IOC_ALLOC.
Add generic helper dmabuf ops for dma heaps, so we can reduce
the amount of duplicative code for the exported dmabufs.
This code is an evolution of the Android ION implementation, so
thanks to its original authors and maintainters:
Rebecca Schultz Zavin, Colin Cross, Laura Abbott, and others!
C
This patch adds system heap to the dma-buf heaps framework.
This allows applications to get a page-allocator backed dma-buf
for non-contiguous memory.
This code is an evolution of the Android ION implementation, so
thanks to its original authors and maintainters:
Rebecca Schultz Zavin, Colin Cr
This adds a CMA heap, which allows userspace to allocate
a dma-buf of contiguous memory out of a CMA region.
This code is an evolution of the Android ION implementation, so
thanks to its original author and maintainters:
Benjamin Gaignard, Laura Abbott, and others!
Cc: Laura Abbott
Cc: Benjami
Here is another RFC of the dma-buf heaps patchset Andrew and I
have been working on which tries to destage a fair chunk of ION
functionality.
The patchset implements per-heap devices which can be opened
directly and then an ioctl is used to allocate a dmabuf from the
heap.
The interface is simila
Hi,
On Thu, Mar 28, 2019 at 1:27 PM Ezequiel Garcia wrote:
>
> On Thu, 2019-03-28 at 10:17 -0700, Douglas Anderson wrote:
> > From: Sean Paul
> >
> > This patch adds a new subnode to simple-panel allowing us to override
> > the typical timing expressed in the panel's display_timing.
> >
> > Cha
Daniel Vetter writes:
> On Thu, Mar 28, 2019 at 03:12:23PM +0100, Neil Armstrong wrote:
>> On 27/03/2019 20:06, Eric Anholt wrote:
>> > Neil Armstrong writes:
>> >
>> >> Hi,
>> >>
>> >> On 26/03/2019 21:40, Vasily Khoruzhick wrote:
>> >>> Hi,
>> >>>
>> >>> So what's the status of it?
>> >>
>> >
On Thu, Mar 28, 2019 at 09:59:12PM +0100, Daniel Vetter wrote:
> On Thu, Mar 28, 2019 at 7:30 PM Sean Paul wrote:
> >
> >
> > Hi Da.*,
> > Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my
> > build
> > scripts to get a bit more variety in them, hopefully catch something lik
On Wed, Mar 27, 2019 at 07:15:00PM +0100, Daniel Vetter wrote:
> On Tue, Mar 26, 2019 at 04:44:54PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch adds a new drm helper library to help drivers implement
> > self refresh. Drivers choosing to use it will register crtcs and
> > will
On Thu, Mar 28, 2019 at 7:30 PM Sean Paul wrote:
>
>
> Hi Da.*,
> Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my build
> scripts to get a bit more variety in them, hopefully catch something like this
> before it gets sent out.
I really want to get this all sorted out with
On Thu, 2019-03-28 at 10:17 -0700, Douglas Anderson wrote:
> From: Sean Paul
>
> This patch adds a new subnode to simple-panel allowing us to override
> the typical timing expressed in the panel's display_timing.
>
> Changes in v2:
> - Split out the binding into a new patch (Rob)
> - display-t
Add Plane Gamma Register definitions for ICL+
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed029
Implement plane CSC on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 86
drivers/gpu/drm/i915/intel_display.c | 3 ++
3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i9
Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 504c046..22790b4 100644
--- a
Update the plane gamma and degamma feature in the
plane state and eventually program to PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 6 ++
drivers/gpu/drm/i915/intel_display.c | 6 +-
3 files changed, 1
Add Plane color capabilties, support for
degamma and gamma added.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 12 +---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 11 ++
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40bde4b..657232bd 100644
---
Add register definitions for ICL Plane Degamma.
v2: Fixed register definitions for Degamma Index, spotted
by Matt Roper.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i91
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/
Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index afb1d00..504c046 100644
--- a
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all
color operations consolidated at one place. N
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documen
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
v
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by
Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Adde
This is how a typical display color hardware pipeline looks like:
+---+
|RAM|
| +--++-++-+ |
| | FB 1 || FB 2 || FB N| |
| +--++-++-+
On Thu, Mar 21, 2019 at 04:27:06PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> Le mercredi 20 mars 2019 à 09:56 -0700, Eric Anholt a écrit :
> > Paul Kocialkowski writes:
> >
> > > The firstopen DRM driver hook was initially used to perform hardware
> > > initialization, which is now considered le
Hi Da.*,
Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my build
scripts to get a bit more variety in them, hopefully catch something like this
before it gets sent out.
drm-misc-next-2019-03-28-1:
drm-misc-next for 5.2:
UAPI Changes:
- None
Cross-subsystem Changes:
- None
On Thu, 28 Mar 2019 19:10:07 +0100
Andrey Konovalov wrote:
> > > Signed-off-by: Andrey Konovalov
> > > ---
> > > ipc/shm.c | 2 ++
> > > mm/madvise.c | 2 ++
> > > mm/mempolicy.c | 5 +
> > > mm/migrate.c | 1 +
> > > mm/mincore.c | 2 ++
> > > mm/mlock.c | 5 +
> > > mm/
On Thu, 28 Mar 2019, Jani Nikula wrote:
> Hi Dave and Daniel, a fairly normal fixes pull.
>
> drm-intel-fixes-2019-03-28:
> drm/i915 fixes for v5.2-rc3:
> - fix mmap range checks
> - fix gvt ppgtt mm LRU list access races
> - fix selftest error pointer check
> - fix a macro definition (pre-emptive
On Wed, 20 Mar 2019 09:20:56 +0100, Lubomir Rintel wrote:
> There's a generic compatible string and the driver will work on a MMP2 as
> well, using the same binding.
>
> Signed-off-by: Lubomir Rintel
>
> ---
> Changes since v2:
> - Order marvell,armada-lcdc after the model-specific strings.
>
>
On Fri, 29 Mar 2019, Jagadeesh Pagadala wrote:
> On Thu, Mar 28, 2019 at 04:12:10PM +0200, Laurent Pinchart wrote:
>> Hi Jagadeesh,
>>
>> On Thu, Mar 28, 2019 at 09:32:06PM +0530, Jagadeesh Pagadala wrote:
>> > On Thu, Mar 28, 2019 at 08:51:24AM +0200, Laurent Pinchart wrote:
>> > > On Thu, Mar 2
Hi Dave, Daniel,
New stuff for 5.2:
amdgpu:
- Switch to HMM for userptr (reverted until HMM fixes land)
- New experimental SMU 11 replacement for powerplay for vega20 (not enabled by
default)
- Initial RAS support for vega20
- BACO support for vega12
- BACO fixes for vega20
- Rework IH handling
Hi Dave and Daniel, a fairly normal fixes pull.
drm-intel-fixes-2019-03-28:
drm/i915 fixes for v5.2-rc3:
- fix mmap range checks
- fix gvt ppgtt mm LRU list access races
- fix selftest error pointer check
- fix a macro definition (pre-emptive for potential further backports)
- fix one AML SKU ULX
https://bugs.freedesktop.org/show_bug.cgi?id=108940
--- Comment #20 from udo ---
Correction: 4.19.12.
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https://bugs.freedesktop.org/show_bug.cgi?id=108940
--- Comment #19 from udo ---
In my kernel history 4.9.12 is the first kernel that shows the WARNING in
dmesg.
--
You are receiving this mail because:
You are the assignee for the bug.___
dri-devel ma
Hi,
On Mon, Mar 12, 2018 at 1:35 AM Thierry Reding wrote:
>
> On Thu, Feb 08, 2018 at 12:48:47PM -0500, Sean Paul wrote:
> > Hello!
> >
> > Here's v3 of the set. I've reintroduced the single display timing node
> > in the dt binding from v1, and left the improved docs and patch split
> > from v2.
Let's document the display timings that jerry has been using out in
the field. This uses the standard blankings but a slightly slower
clock rate, thus getting a refresh rate 58.3 Hz.
NOTE: this won't really do anything except cause DRM to properly
report the refresh rate since vop_crtc_mode_fixup
Just like rk3288-veyron-jerry, we want to be able to use one of the
fixed PLLs in the system to make the pixel clock for minnie.
Specifying these timings matches us with how the display is used on
the downstream Chrome OS kernel. See https://crrev.com/c/323211.
Unlike jerry, this CL actually cha
Convert the Innolux n116bge from using a fixed mode to specifying a
display timing with min/typ/max values.
Note that the n116bge's datasheet doesn't fit too well into DRM's way
of specifying things. Specifically the panel's datasheet just
specifies the vertical blanking period and horizontal bla
From: Sean Paul
This patch adds an override mode for kevin devices. The mode increases
both back porches to allow a pixel clock of 2kHz as opposed to the
'typical' value of 252750kHz. This is needed to avoid interference with
the touch digitizer on these laptops.
Cc: Doug Anderson
Cc: Eric
From: Sean Paul
This patch adds a new subnode to simple-panel allowing us to override
the typical timing expressed in the panel's display_timing.
Changes in v2:
- Split out the binding into a new patch (Rob)
- display-timings is a new section (Rob)
- Use the full display-timings subnode inste
Convert the AUO b101ean01 from using a fixed mode to specifying a
display timing with min/typ/max values.
The AUO b101ean01's datasheet says:
* Vertical blanking min is 12
* Horizontal blanking min is 60
* Pixel clock is between 65.3 MHz and 75 MHz
The goal here is to be able to specify the prope
From: Sean Paul
This patch adds the ability to override the typical display timing for a
given panel. This is useful for devices which have timing constraints
that do not apply across the entire display driver (eg: to avoid
crosstalk between panel and digitizer on certain laptops). The rules are
I'm reviving Sean Paul's old patchset to get mode support in device
tree. The cover letter for his v3 is at:
https://lists.freedesktop.org/archives/dri-devel/2018-February/165162.html
I've pulled together the patches that didn't land in v3, addressed
outstanding feedback, and reposted. Atop them
https://bugs.freedesktop.org/show_bug.cgi?id=108940
--- Comment #18 from udo ---
I see this WARNING on boot with various kernels, currently 4.19.30.
What can I try to avoid this WARNING?
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On Wed, Mar 27, 2019 at 09:20:00AM +0100, Guido Günther wrote:
> Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.
>
> Signed-off-by: Guido Günther
> Reviewed-by: Sam Ravnborg
> ---
> .../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +++
> 1 file changed, 29 ins
Hi Wen,
On Thu, Mar 28, 2019 at 03:56:58AM +, Wen He wrote:
> When we running DDR benchmark test will able to observed flicker issue
> in 4k@60 resolution on monitor. In LS1028A SoC, need increasing DP500
> priority to avoid that issue.
>
> Signed-off-by: Wen He
> ---
> drivers/gpu/drm/arm/
On Fri, Mar 22, 2019 at 9:56 PM Reza Arbab wrote:
> If the scaling loop in drm_fb_helper_single_fb_probe() only finds
> supported depths greater than what it's looking for, it will set
> sizes.surface_depth = 0. This broke my udl device:
>
> [drm] test CRTC 0 primary plane
> udl 3-9.1:1.0: drm_fb
The binner BO is a pre-requisite to GPU operations, so we must ensure
that it is always allocated when the GPU is in use. Currently, we are
allocating it at probe time and liberating/allocating it during runtime
pm cycles.
First, since the binner buffer is only required for GPU rendering, it's
a w
The firstopen DRM driver hook was initially used to perform hardware
initialization, which is now considered legacy. Only a single user of
firstopen remains at this point (savage).
In some specific cases, non-legacy drivers may also need to implement
these hooks. For instance on VC4, we need to al
Changes since v2:
* Removed deprecated sentence about fristopen;
* Added collected Reviewed-By tags.
Changes since v1:
* Squashed the two final patches into one.
Paul Kocialkowski (2):
drm/file: Rehabilitate the firstopen hook for non-legacy drivers
drm/vc4: Allocated/liberate the binner BO a
On Thu, Mar 28, 2019 at 4:33 PM Sean Paul wrote:
>
>
> Hi Da.*,
> This week's -next pull is here! A couple of things to monitor in this one, the
> skip_vt_switch default and the DRM_DISPLAY_INFO_LEN removal (which definitely
> shouldn't be used by anyone, but stranger things have happened).
>
> Pl
On Thu, 14 Mar 2019 13:26:19 +0100, Paul Cercueil wrote:
> The GPM940B0 is a 3.0" 320x240 24-bit TFT LCD panel.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Notes:
> v2: New patch
>
> .../devicetree/bindings/display/panel/giantplus,gpm940b0.txt | 12
>
> 1 file changed, 12 inse
On Thu, 14 Mar 2019 13:26:18 +0100, Paul Cercueil wrote:
> The LS020B1DD01D is a 2.0" 240x160 16-bit TFT LCD panel.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Notes:
> v2: New patch
>
> .../devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt | 12
>
> 1 file changed, 12
On 2019-03-28 4:18 p.m., Christian König wrote:
> Am 28.03.19 um 14:50 schrieb Lionel Landwerlin:
>> On 25/03/2019 08:32, Chunming Zhou wrote:
>>> From: Christian König
>>>
>>> Use the dma_fence_chain object to create a timeline of fence objects
>>> instead of just replacing the existing fence.
>>
Hi Da.*,
This week's -next pull is here! A couple of things to monitor in this one, the
skip_vt_switch default and the DRM_DISPLAY_INFO_LEN removal (which definitely
shouldn't be used by anyone, but stranger things have happened).
Please pull.
drm-misc-next-2019-03-28:
drm-misc-next for 5.2:
U
Quoting Dave Airlie (2019-03-28 04:09:56)
> On Mon, 25 Mar 2019 at 22:49, Joonas Lahtinen
> wrote:
> >
> > Hi Dave & Daniel,
> >
> > First batch of features for 5.2, tagged last week.
>
> I asked on irc, but got no answer I saw,
> /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/i915_gem_c
On Wed, 13 Mar 2019 15:10:30 +0100, Neil Armstrong wrote:
> The Amlogic G12A has a slighly different Power Control, but uses the
> same address space and sysctrl registers.
>
> Signed-off-by: Neil Armstrong
> ---
> .../devicetree/bindings/power/amlogic,meson-gx-pwrc.txt | 4 +++-
> 1 file
Am 28.03.19 um 14:50 schrieb Lionel Landwerlin:
On 25/03/2019 08:32, Chunming Zhou wrote:
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
v4: a
When called during unloading, the function radeon_gart_unbind() may
complain about the GART not being initialized.
TTM calls the function radeon_gart_unbind() as part of its finish
procedure and expects the GART structure to be initialized. As the radeon
driver calls radeon_gart_fini() before fini
On Wed, 13 Mar 2019 15:10:29 +0100, Neil Armstrong wrote:
> The Amlogic G12A SoC has a slighly modified DW-HDMI Glue with
> support for HDMI 2.1 and a different DW-HDMI register access.
>
> Signed-off-by: Neil Armstrong
> ---
> .../devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 4 ++
On Wed, 13 Mar 2019 15:10:28 +0100, Neil Armstrong wrote:
> The Amlogic G12A VPU is very similar to the Amlogic GXM VPU but with :
> - an enhanced plane blender, with up to 3 OSD planes
> - support for AFBC 1.2 decoder (for Bifrost GPU)
> - support display mode up to 4k60@75Hz
>
> Signed-off-by: N
#x27;drm-misc-next-2019-03-21' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2019-03-25 11:05:12
+0100)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2019-03-28
for you to fetch changes up to a01b2c6f47d86c7d1a9fa8
Hi Sean,
url:
https://github.com/0day-ci/linux/commits/Sean-Paul/drm-Add-helpers-to-kick-off-self-refresh-mode-in-drivers/20190327-194853
smatch warnings:
drivers/gpu/drm/drm_self_refresh_helper.c:105
drm_self_refresh_helper_entry_work() error: uninitialized symbol 'ret'.
#
https://github.
We don't want to overwrite "ret", it already holds the correct error
code. The "regmap" variable might be a valid pointer as this point.
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 -
1 file changed, 1 deletion(
On Thu, Mar 28, 2019 at 03:12:23PM +0100, Neil Armstrong wrote:
> On 27/03/2019 20:06, Eric Anholt wrote:
> > Neil Armstrong writes:
> >
> >> Hi,
> >>
> >> On 26/03/2019 21:40, Vasily Khoruzhick wrote:
> >>> Hi,
> >>>
> >>> So what's the status of it?
> >>
> >> We are waiting on ARM to give a fee
On 27/03/2019 20:06, Eric Anholt wrote:
> Neil Armstrong writes:
>
>> Hi,
>>
>> On 26/03/2019 21:40, Vasily Khoruzhick wrote:
>>> Hi,
>>>
>>> So what's the status of it?
>>
>> We are waiting on ARM to give a feedback on the ARM GPU tile modifier,
>> see https://patchwork.freedesktop.org/patch/292
On 25/03/2019 08:32, Chunming Zhou wrote:
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
v4: add unorder point check, print a warn calltrace
S
On 28/03/2019 13:08, Chunming Zhou wrote:
在 2019/3/28 20:53, Lionel Landwerlin 写道:
On 25/03/2019 08:32, Chunming Zhou wrote:
v2: individually allocate chain array, since chain node is free
independently.
v3: all existing points must be already signaled before cpu perform
signal operation,
On Tue, Mar 12, 2019 at 12:13:41PM -0600, Jordan Crouse wrote:
> Describe the zap-shader node that defines a reserved memory region
> to store the zap shader.
>
> Signed-off-by: Jordan Crouse
> ---
>
> Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
> 1 file changed, 7 insert
Hi Laurent,
On Thu, Mar 28, 2019 at 09:07:15AM +0200, Laurent Pinchart wrote:
> The V4L2 API is missing the 32-bit RGB formats for the ABGR, XBGR, RGBA
> and RGBX component orders. Add them, using the same 4CCs as DRM.
>
> Signed-off-by: Laurent Pinchart
> ---
> .../media/uapi/v4l/pixfmt-packed-
在 2019/3/28 20:53, Lionel Landwerlin 写道:
> On 25/03/2019 08:32, Chunming Zhou wrote:
>> v2: individually allocate chain array, since chain node is free
>> independently.
>> v3: all existing points must be already signaled before cpu perform
>> signal operation,
>> so add check condition for
On 25/03/2019 08:32, Chunming Zhou wrote:
v2: individually allocate chain array, since chain node is free independently.
v3: all existing points must be already signaled before cpu perform signal
operation,
so add check condition for that.
v4: remove v3 change and add checking to prevent ou
On Tue, Mar 19, 2019 at 4:26 PM Maxime Ripard wrote:
>
> On Mon, Mar 11, 2019 at 08:28:22PM +0530, Jagan Teki wrote:
> > On Mon, Mar 11, 2019 at 7:39 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Mar 07, 2019 at 09:24:02PM +0530, Jagan Teki wrote:
> > > > On Thu, Mar 7, 2019 at 9:09 PM Maxime
On 28.03.2019 01:07, Life is hard, and then you die wrote:
> Hi Andrzej,
>
> On Wed, Mar 27, 2019 at 03:13:37PM +0100, Andrzej Hajda wrote:
>> +cc: dri-devel
>>
>> On 27.03.2019 02:48, Ronald Tschalär wrote:
>>> commit d6abe6df706c66d803e6dd4fe98c1b6b7f125a56 (drm/bridge:
>>> sil_sii8620: do not
On Mon, Mar 25, 2019 at 09:26:31AM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/virtio/virtgpu_ttm.c: In function 'virtio_gpu_init_mem_type':
> drivers/gpu/drm/virtio/virtgpu_ttm.c:117:28: warning:
> variable 'vgdev' set but not used [-Wunused-but-
> From: Nathan Chancellor
>
> [ Upstream commit 672e78cab819ebe31e3b9b8abac367be8a110472 ]
>
> Clang warns when an expression that equals zero is used as a null
> pointer constant (in lieu of NULL):
Fixes warning, with unsupported compiler; not a serious bug. Plus, not
a minimal fix.
On Tue, Mar 26, 2019 at 06:55:30PM +0100, Noralf Trønnes wrote:
> This moves the modesetting code from drm_fb_helper to drm_client so it
> can be shared by all internal clients.
>
> I have also added a client display abstraction and a bootsplash example
> client to show where this might be heading
On Tue, Mar 26, 2019 at 06:55:35PM +0100, Noralf Trønnes wrote:
> The values are already present in the modeset.
>
> This is done in preparation for the removal of struct drm_fb_helper_crtc.
>
> Signed-off-by: Noralf Trønnes
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_fb_helper.c
On Tue, Mar 26, 2019 at 06:55:43PM +0100, Noralf Trønnes wrote:
> drm_fb_helper_is_bound() is used to check if DRM userspace is in control.
> This is done by looking at the fb on the primary plane. By the time
> fb-helper gets around to committing, it's possible that the facts have
> changed.
>
>
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: Wangyan Wang
>
> V7 adopt maintainer's suggestion.
> Here is the change list between V6 & V7
>
> 1. use readl directly & delete hdmi_phy->pll_rate in
> mtk_hdmi_pll_recalc_rate().
> in "drm/mediatek: recalculate hdmi ..."
>
> 2. de
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