Hi Sean,
On Fri, Mar 10, 2017 at 1:32 PM, Sean Paul wrote:
>
> From: Tomasz Figa
>
> Since we take the ownership of drvdata, the master driver does not have
> any means of accessing its own data from unbind callback and all it can
> do is calling the analogix unbind callback. However it might be
https://bugs.freedesktop.org/show_bug.cgi?id=99923
--- Comment #11 from thedribbleo...@gmail.com ---
(In reply to Ernst Sjöstrand from comment #8)
> R600_DEBUG=sisched?
Also, I tried using the R600_debug command upon Steam startup, and Siched did
make a positive performance impact after all.
--
https://bugs.freedesktop.org/show_bug.cgi?id=99923
--- Comment #10 from sephirot...@gmail.com ---
I have the same issue. My GPU is a 7950. I am using Debian packages. I see the
issue with Mesa 17.0.1/LLVM 4. With Mesa 13.0.5/LLVM 3.9 the issue is not
present. This is also at the lowest settings po
From: Tomasz Figa
This patch adds a function that master driver can call at shutdown time
in case there is some cleanup work to do. The function will then call
back to platform_data .cleanup() callback to let the master driver do
the platform-specific work.
Cc: Kristian H. Kristensen
Cc: Brian
From: zain wang
We do not have to drive the display when it is in PSR mode, so we can
save some power by disabling active VOP windows, until a next PSR flush
turns them back on.
Cc: Kristian H. Kristensen
Signed-off-by: zain wang
Signed-off-by: Tomasz Figa
Signed-off-by: Douglas Anderson
Sig
From: Douglas Anderson
Some of the platform-specific stuff in rockchip_dp_poweron() needs to
happen before the generic code. Some needs to happen after. Let's
split the callback in two.
Specifically we can't start doing PSR work until _after_ the whole
controller is up, so don't set the enable
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_
From: Lin Huang
AUX errors are caused by many different reasons. We may not know what
happened in aux channel on failure, so let's reset aux channel if some
errors occurred.
Cc: 征增 王
Cc: Douglas Anderson
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/a
From: Tomasz Figa
Currently PSR flush is triggered from CRTC's .atomic_begin() callback,
which is executed after modeset disables and enables and before plane
updates are committed. Since PSR flush and re-enable can be triggered
asynchronously by external sources (input event, delayed work), it c
From: Douglas Anderson
The code in analogix_dp_transfer() that was supposed to print out:
AUX CH error happened
Was actually dead code. That's because the previous check (whether
the interrupt status indicated any errors) would have hit for all
errors anyway.
Let's combine the two error check
From: Tomasz Figa
Current implementation of unbind dereferences the drvdata pointer
assuming that it's its own data, however the ownership belongs to the
analogix code, which means that the pointer is dereferenced with wrong
type. Fix this by using the recently added platform data .cleanup()
call
From: zain wang
The STRM_VALID bit in register ANALOGIX_DP_SYS_CTL_3 may be unstable,
so we may hit the error log "Timeout of video streamclk ok" since
checked this unstable bit.
In fact, we can go continue and the streamclk is ok if we wait enough time,
it does no effect on display.
Let's change
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analo
From: zain wang
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to Exynos:
on Exynos edp phy,
BIT 7 MASTER_VID_FUNC_EN_N
BIT 6 reserved
BIT 5 SLAVE_VID_FUNC_EN_N
on Rockchip edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
BIT
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 25 +--
1 file changed, 14 i
From: Douglas Anderson
The current user of the analogix power_off is "analogix_dp-rockchip".
That driver does this:
- deactivate PSR
- turn off a clock
Both of these things (especially deactive PSR) should be done before
we turn the PHY power off and turn off analog power. Let's move the
callba
From: Tomasz Figa
Since we take the ownership of drvdata, the master driver does not have
any means of accessing its own data from unbind callback and all it can
do is calling the analogix unbind callback. However it might be
necessary to do some clean up in the master driver before we really
unb
From: Tomasz Figa
We have to disable PSR before shutdown to avoid any asynchronous PSR
code to interfere with Rockchip DRM device shutdown. We use the recently
added analogix_dp_shutdown() function and rockchip_dp_cleanup() we
already use for unregistering PSR at unbind time.
Cc: Kristian H. Kri
From: zain wang
It's too early to detect fast link training, if other step after it failed,
we will set fast_link flag to 1, and retry set_bridge again. In this case
we will power down and power up panel power supply, and we will do fast link
training since we have set fast_link flag to 1. In fac
From: zain wang
Panel would reset it's setting when it power down. It would forget the last
successed link training setting. So we can't use the last successful link
training setting to do fast link training. Let's reset fast_train_enable in
analogix_dp_bridge_disable();
Cc: Stéphane Marchesin
From: zain wang
Enhanced mode is required by the eDP 1.2 specification, and not doing it early
could result in a period of time where we have a link transmitting idle packets
without it. Since there is no reason to disable it, we just enable it at the
beginning of link training and then keep it o
From: zain wang
We currently wait for the panel to mirror our intended PSR state
before continuing on both PSR enter and PSR exit. This is really
only important to do when we're entering PSR, since we want to
be sure the last frame we pushed is being served from the panel's
internal fb before shu
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 65 +-
drivers/gpu/drm/bridge/
From: Mark Yao
Some encoder have a crc verification check, crc check fail if
input and output data is not equal.
That means encoder input and output need use same color depth,
vop can output 10bit data to encoder, but some panel only support
8bit depth, that would make crc check die.
So pre dit
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu
Now that the spinlocks and timers are gone, we can remove the psr
worker located in rockchip's analogix driver and do the enable/disable
directly. This should simplify the code and remove races on disable.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Sean Paul
---
drivers/gpu/drm/rockchip/an
From: Lin Huang
We only allocated 1ms to detect the hpd signal before, it too short to detect
a short pulse (hpd signal), extend it to 100ms.
Cc: Stéphane Marchesin
Cc: 征增 王
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +-
1 fi
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++
1 file cha
From: zain wang
We would meet a short black screen when exit PSR with the full link
training, In this case, we should use fast link train instead of full
link training.
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 142 +
From: zain wang
There some different bit between Rockchip and Exynos in register "AUX_PD",
So let's fix the incorrect operations about it.
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 116 --
From: zain wang
Add a lock to vop to avoid disabling the crtc while waiting for a line
flag while enabling psr. If we disable in the middle of waiting for the
line flag, we'll end up timing out or worse.
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/rockchip/rockchip_d
From: Lin Huang
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +--
1 file cha
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Cc: Tomeu Vizoso
Cc: Sean Paul
Signed-off-by: zain wang
Signed-off-by: Caesar Wang
[seanpaul fixed up the
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Yakir Yang
[seanpaul changed timeout loop to a readx poll]
Si
Instead of using timer and spinlocks, use delayed_work and
mutexes for rockchip psr. This allows us to make blocking
calls when enabling/disabling psr (which is sort of important
given we're talking over dpcd to the display).
Cc: Caesar Wang
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Sean P
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 10 --
drivers/gpu/drm/bridge/analogix/analogix_dp_r
From: zain wang
The bridge does not need to be powered in analogix_dp_bind(), so
remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
as well as their power-off counterparts.
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Caesar Wang
[the patch originally
From: Douglas Anderson
The comments in analogix_dp_init_aux() claim that we're disabling aux
channel retries, but then right below it for Rockchip it sets them to
3. If we actually need 3 retries for Rockchip then we could adjust
the comment, but it seems more likely that we want the same retry
From: Ørjan Eide
When mapping external DMA-bufs through the PRIME mmap call, we might be
given an offset which has to be respected. However for the internal DRM
GEM mmap path, we have to ignore the fake mmap offset used to identify
the buffer only. Currently the code always zeroes out vma->vm_pgo
From: Tomasz Figa
Current code implements prepare_fb and cleanup_fb callbacks only to
grab/release fb references, which is already done by atomic framework
when creating/destryoing plane state. Also there are some unused fields
vop and vop_win structs. Let's remove these unused bits.
Signed-off-
From: Haixia Shi
The prime fd to handle ioctl was not used with rockchip before. Support
was added in order to pass graphics_Gbm and to support potential uses
within Chrome OS (e.g. zero-copy video decode, camera).
Signed-off-by: Haixia Shi
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1
From: zain wang
There's a race between when bridge_disable and when vop_crtc_disable
are called. If the flush timer triggers a new psr work between these,
we will operate eDP without power shutdowned by bridge_disable. In this
case, moving activate/deactivate to enable/disable bridge to avoid it.
Change the mode for Sharp lq123p1jx31 panel to something more
rockchip-friendly such that we can use the fixed PLLs to
generate the pixel clock
Cc: Chris Zhong
Cc: Stéphane Marchesin
Signed-off-by: Sean Paul
---
drivers/gpu/drm/panel/panel-simple.c | 7 ---
1 file changed, 4 insertions(+),
Despite our best intentions (and we did a decent job this time around) of
submitting
upstream first for the Chromebook Plus, we had a number of patches slip through
the
cracks. This series includes all but one of those patches. The outlier breaks my
veyron board, so I dropped it.
The patches hav
Hi Linus,
These are the drm fixes I've collected for rc2. Mostly i915 GVT only
fixes, along with a single EDID fix, some mxsfb fixes and a few minor
amd fixes.
Thanks,
Dave.
The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
Talk to Jonas (jadahl) on irc, he had 3 mutters running and on hotplug
all 3 of them were diving into the connector getting code. Now I think
we can avoid this in userspace by not probing when not owning the VT,
but it's still messy behaviour.
It looks like one thread does a getconnector, this fil
>
> As far as I can see the only functionality we are missing here is:
>
> void sync_file_signal(struct sync_file *sync_file, struct dma_fence *fence)
> {
> dma_fence_put(sync_file->fence);
> sync_file->fence = fence;
> }
>
> We probably should do this atomically, but that is only a matter
On Wed, Feb 22, 2017 at 10:23:18AM +0200, Jani Nikula wrote:
>
> [Your MUA messed up the quoting, FTFY below.]
>
> On Wed, 22 Feb 2017, "Navare, Manasi D" wrote:
> > > On Fri, 17 Feb 2017, Manasi Navare wrote:
> > >> Display stream compression is supported on DP 1.4 DP devices. This
> > >> pat
https://bugs.freedesktop.org/show_bug.cgi?id=100141
--- Comment #1 from Michel Dänzer ---
It's not the amdgpu driver's responsibility to perform the reboot. It's
possible that an amdgpu bug somehow prevents the reboot from occurring though.
Does this problem not happen when the amdgpu driver is b
On Fri, Mar 10, 2017 at 12:41:30AM +, Emil Velikov wrote:
> On 9 March 2017 at 22:46, Chris Wilson wrote:
> > ./include/drm/drm_pci.h:76:64: warning: ‘struct platform_device’ declared
> > inside parameter list will not be visible outside of this definition or
> > declaration
> > extern int
Am 10.03.2017 um 00:19 schrieb Dave Airlie:
Completely agree, problem here is that this isn't documented like this in
the Vulkan specification as far as I know.
(I'm adding dri-devel, since I think Intel folks have looked into some
of this already,
and we might need to make some common functiona
On 9 March 2017 at 22:46, Chris Wilson wrote:
> ./include/drm/drm_pci.h:76:64: warning: ‘struct platform_device’ declared
> inside parameter list will not be visible outside of this definition or
> declaration
> extern int drm_platform_init(struct drm_driver *driver, struct
> platform_device *
On Thu, Mar 9, 2017 at 6:36 PM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote:
>> Some Allwinner SoCs have two display pipelines (frontend -> backend ->
>> tcon).
>>
>> Previously we only supported one pipeline. This patch extends the
>> current driver
Hi Maxime,
This is part 3 of my sun4i drm clean up series. In this part support
for 2 display pipelines is added, after some more code cleanups and
restructuring.
While this series enables the second display pipeline, there's no
usable output at the moment. For the A31, the second TCON's panel
in
On Thu, Mar 09, 2017 at 09:31:33AM +0100, Heiko Stuebner wrote:
> Am Mittwoch, 8. März 2017, 19:10:50 CET schrieb Brian Norris:
> > Another random point of contention (not worth too much, as the pattern
> > is already set), but why do these deserve DT properties at all? The
> > device already has a
On Thu, Mar 9, 2017 at 6:58 PM, Maxime Ripard
wrote:
> On Wed, Mar 08, 2017 at 11:51:39AM +0800, Chen-Yu Tsai wrote:
>> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
>> wrote:
>> > Even though that mux is undocumented, it seems like it needs to be set to 1
>> > when using composite, and 0 when us
On Thu, Mar 9, 2017 at 6:59 PM, Maxime Ripard
wrote:
> 1;4601;0c
> On Wed, Mar 08, 2017 at 11:35:39AM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
>> wrote:
>> > The A10s has an HDMI controller connected to the second TCON channel. Add
>> > it to our DT.
>
Hi,
On Thu, Mar 09, 2017 at 02:02:54AM +0100, Heiko Stuebner wrote:
> Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris:
> > On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote:
> > > There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
> > > only one PHY can con
Some Allwinner SoCs have 2 display pipelines, as in 2 of each
components, including the frontend, backend, TCON, and any other
extras.
As the backend and TCON are always paired together and form the CRTC,
we need to know which backend or TCON we are currently probing, so we
can pair them when init
On 03/09/2017 08:58 PM, Daniel Vetter wrote:
On Thu, Mar 9, 2017 at 6:57 PM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for using sync fences as prefences and
postfences for host1x job submissions. The patches are available
as a git repository at
https://github.com/cyndis/
The backporch programmed into the tcon registers is actually the
backporch + hsync length from the display timings, as indicated in
the interface timing diagrams found in the user manual of the A31
and A33 SoCs.
The comments for channel 0 mistakenly describe the discrepancy as
TCON backporch = fro
Hi Neil,
On 08-03-2017 12:12, Neil Armstrong wrote:
>
> Hi Jose,
>
> It seems here that we only have the RGB444<->YUV444 8bit tables, from the
> Amlogic
> source I have the following for 10bit, 12bit and 16bit for itu601 :
>
> static const u16 csc_coeff_rgb_out_eitu601_10b[3][4] = {
> { 0x
A pointer to the underlying tcon of the crtc was added to the sun4i_crtc
structure in "drm/sun4i: Add backend and tcon pointers to sun4i_crtc".
However the crtc init function was still using the copy from sun4i_drv
to set drm_crtc.port. This was an oversight when the patches were
reordered.
Switch
On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote:
> There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
> only one PHY can connect to DP controller at one time, the other should
> be disconnected. The GRF_SOC_CON26 register has a switch bit to do it,
> set this bit means
Hello,
Le 09/03/2017 à 15:28, Jose Abreu a écrit :
> Hi Romain,
>
>
> On 08-03-2017 08:15, Romain Perier wrote:
>> Currently, the irq handler that monitores changes for HPD anx RX_SENSE
>> relies on the status of the bridge for updating the status of the HPD.
>> The update is done only when the b
On Wed, Mar 08, 2017 at 09:15:24AM +0100, Romain Perier wrote:
> - dw_hdmi_update_power() will be called. As hdmi->force will be equal to
> DRM_FORCE_UNSPECIFIED the function will rely on hdmi->rxsense. This
> field has not been updated by the irq handler, so it will be false and
> DRM_FORCE_ON won
The drm_encoder structure provides us with a pointer to the crtc
currently tied to the encoder. Subsequently we can extract the
tcon and backend pointers from our crtc structure, instead of
getting it directly from the sun4i_drv structure.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/su
Hi Romain,
On 08-03-2017 08:15, Romain Perier wrote:
> Currently, the irq handler that monitores changes for HPD anx RX_SENSE
> relies on the status of the bridge for updating the status of the HPD.
> The update is done only when the bridge is enabled.
>
> However, on Rockchip platforms we have f
The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.
Add device nodes and of graph nodes describing this relationship.
Signed-off-by: Chen-Yu T
Some Allwinner SoCs have two display pipelines (frontend -> backend ->
tcon).
Previously we only supported one pipeline. This patch extends the
current driver to support two. It extends the tcon and backend pointers
in sun4i_drv into arrays, and makes the related bind functions store
the pointer i
The TCON driver calls sun4i_tcon_init_regmap and sun4i_tcon_init_clocks
in its bind function. The former creates a regmap and writes to several
register to clear its configuration to a known default. The latter
initializes various clocks. This includes enabling the bus clock for
register access and
Some Allwinner SoCs have 2 display pipelines, as in 2 of each
components, including the frontend, backend, TCON, and any other
extras.
As the backend and TCON are always paired together and form the CRTC,
we need to know which backend or TCON we are currently probing, so we
can pair them when init
Thanks for your tips and links Philipp and Russell!
My distro of choice is Arch and so really I should try to install the
patched git kernel "the Arch way" so my first question is, does anyone
on this list have an Arch PKGBUILD script to create a linux (4.x) git
kernel package for imx6 alikes?
If
sun4i_layer only controls the backend hardware block of the display
pipeline.
Pass pointers to the underlying backend in the layer init function,
instead of trying to fetch it from the drm_device structure. This
avoids the headache of trying to figure out which device the layers
actually belong to
sun4i_crtc controls the backend and tcon hardware blocks of the display
pipeline.
Pass pointers to the underlying devices into the crtc init function,
instead of trying to fetch them from the drm_device structure. This
avoids the headache of trying to figure out which devices the crtc
is actually
tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.
Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/b
Hi all,
After merging the drm-misc tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
In file included from drivers/gpu/drm/drm_pci.c:29:0:
include/drm/drm_pci.h:76:64: warning: 'struct platform_device' declared inside
parameter list
extern int drm_platform_init(stru
https://bugs.freedesktop.org/show_bug.cgi?id=99195
--- Comment #8 from Tim ---
Ok, i tried this on Debian Stretch development branch, and have no hangs.
Tested even in heavy video games. Debian have 13.0.5 version of mesa. But
Chromium with enabled hardware acceleration still hangs whole system a
> Completely agree, problem here is that this isn't documented like this in
> the Vulkan specification as far as I know.
(I'm adding dri-devel, since I think Intel folks have looked into some
of this already,
and we might need to make some common functionality).
"The semaphore must be signaled, o
./include/drm/drm_pci.h:76:64: warning: ‘struct platform_device’ declared
inside parameter list will not be visible outside of this definition or
declaration
extern int drm_platform_init(struct drm_driver *driver, struct platform_device
*platform_device);
Fixes: 23ef59ef6dcc ("drm: Extract drm
Hi Dave,
A few fixes for 4.11.
The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
are available in the git repository at:
git://people.freedesktop.org/~agd5f/linux drm-fixes-4.11
for you to fetch changes up to a5b11dac1f
https://bugs.freedesktop.org/show_bug.cgi?id=100141
Bug ID: 100141
Summary: [AMDGPU][CIK][4.10/4.11-rc1] Regression - Hibernation
does not respect 'reboot' option in /sys/power/disk
Product: DRI
Version: unspecified
Hardwar
From: Thierry Reding
The check for valid syncpoint IDs is off by one. While at it, rewrite
the check to make it more easily understandable.
Signed-off-by: Thierry Reding
---
drivers/gpu/host1x/syncpt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/host1x/syncp
From: Thierry Reding
Each open file descriptor can have any number of contexts associated
with it. To differentiate between these contexts a unique ID is required
and back when these userspace interfaces were introduced, in commit
d43f81cbaf43 ("drm/tegra: Add gr2d device"), the pointer to the co
From: Thierry Reding
IOMMU support is currently not thread-safe, which can cause crashes,
amongst other things, under certain workloads.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/drm.c | 5 +
drivers/gpu/drm/tegra/drm.h | 1 +
drivers/gpu/drm/tegra/gem.c | 12 ++--
On Thu, Mar 9, 2017 at 6:57 PM, Mikko Perttunen wrote:
> Hi everyone,
>
> this series adds support for using sync fences as prefences and
> postfences for host1x job submissions. The patches are available
> as a git repository at
>
> https://github.com/cyndis/linux/tree/host1x-fence-1
>
> and te
tree: git://anongit.freedesktop.org/drm-intel drm-intel-nightly
head: 510c200742ced5a91d07e48220b669a3c9b30c0c
commit: 23ef59ef6dcc9b62bf077490a74df93b3bb0d530 [777/788] drm: Extract
drm_pci.h
config: tile-tilegx_defconfig (attached as .config)
compiler: tilegx-linux-gcc (GCC) 4.6.2
reproduce:
Adds ability to pass sync file based prefences and get back
sync file based postfences during job submission. Both
fence fd's are passed in the `fence` field. A new `flags`
field is used to specify if the prefence should be waited
or a postfence created.
Signed-off-by: Mikko Perttunen
---
includ
Hi everyone,
this series adds support for using sync fences as prefences and
postfences for host1x job submissions. The patches are available
as a git repository at
https://github.com/cyndis/linux/tree/host1x-fence-1
and testing code is available at
https://github.com/cyndis/host1x_test
th
Add an implementation of DMA fences backed by Host1x syncpoints,
an interface to specify a prefence for job submissions.
Before submission, prefences containing only Host1x syncpoints
are waited by pushing wait commands to CDMA, whereas other
fences are CPU-waited.
Signed-off-by: Mikko Perttunen
Add support for sync file-based prefences and postfences
to job submission. Fences are passed to the Host1x implementation.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 69 ++---
1 file changed, 59 insertions(+), 10 deletions(-)
diff -
On 03/09/2017 02:00 AM, Benjamin Gaignard wrote:
> 2017-03-06 17:04 GMT+01:00 Daniel Vetter :
>> On Mon, Mar 06, 2017 at 11:58:05AM +0100, Mark Brown wrote:
>>> On Mon, Mar 06, 2017 at 11:40:41AM +0100, Daniel Vetter wrote:
>>>
No one gave a thing about android in upstream, so Greg KH just dum
Hi Chih-Wei,
On 9 March 2017 at 02:12, Chih-Wei Huang wrote:
> To avoid the warning:
>
> external/libdrm/intel/intel_bufmgr.c:362:20: warning: more '%' conversions
> than data arguments [-Wformat]
> fprintf(stderr, "%s: Mappable aperture size hardcoded to 64MiB\n");
>
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 510c200742ced5a91d07e48220b669a3c9b30c0c
commit: 23ef59ef6dcc9b62bf077490a74df93b3bb0d530 [777/788] drm: Extract
drm_pci.h
config: i386-randconfig-x070-201710 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
rep
+ intel-gfx
+ dri-devl
(missed in in-reply-to)
Regards
Shashank
-Original Message-
From: Sharma, Shashank
Sent: Thursday, March 9, 2017 6:02 PM
To: ville.syrj...@linux.intel.com; conselv...@gmail.com
Cc: Sharma, Shashank
Subject: [PATCH v9] drm/i915: enable scrambling
Geminilake platfo
On Fri, Feb 24, 2017 at 08:19:45PM +0100, Lukas Wunner wrote:
> Fix Thunderbolt-related issues in apple-gmux and vga_switcheroo:
>
> Patch [1/5] ("Recognize Thunderbolt devices") has already been subjected
> to a fair amount of scrutiny over at linux-pci@, I've submitted it 5 times
> total since M
On Thu, Mar 09, 2017 at 07:31:27PM +0800, Chen-Yu Tsai wrote:
> >> Additionally, the mux registers are only valid in the first TCON, meaning
> >> it must available be active in 2 pipeline chips. It's also why we'd pass
> >> "struct drm_device *" instead of "struct sun4i_tcon *".
> >
> > H. That
On Thu, Mar 09, 2017 at 07:20:30PM +0800, Chen-Yu Tsai wrote:
> On Thu, Mar 9, 2017 at 6:36 PM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote:
> >> Some Allwinner SoCs have two display pipelines (frontend -> backend ->
> >> tcon).
> >>
> >> Pre
On Thu, Mar 9, 2017 at 5:55 AM, Lukas Wunner wrote:
> On Wed, Mar 08, 2017 at 03:34:47PM -0500, Alex Deucher wrote:
>> On Wed, Mar 8, 2017 at 12:01 AM, Lukas Wunner wrote:
>> > On Tue, Mar 07, 2017 at 03:30:30PM -0500, Alex Deucher wrote:
>> >> On Fri, Feb 24, 2017 at 2:19 PM, Lukas Wunner wrote
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