Hello all,
I've been trying to use some of the test benches provided from Ettus' site, in
the "fpga/tb" directory. I'm using Quartus II and ModelSim with the latest
version of the fpga code.
I'm assuming that fullchip_tb.v is the test bench for the full fpga. However,
the test bench seem
Hi all,
I'm trying to modify the test bench provided with the standard USRP verilog
code
to work with the latest version of the usrp_std module. I'm using the 2rx 0tx
config.
My problem is that I don't think I'm initializing the usrp_std module properly;
I'm not sure of the order of even
es for the full chip?
Nelson.
- Original Message
> From: Nelson Costa
> To: gnu radio discussion
> Sent: Thu, September 2, 2010 8:14:16 AM
> Subject: [Discuss-gnuradio] More test bench stuff with usrp_std
>
> Hi all,
>
> I'm trying to modify the test ben
