Hi all,
I'm trying to modify the test bench provided with the standard USRP verilog
code
to work with the latest version of the usrp_std module. I'm using the 2rx 0tx
config.
My problem is that I don't think I'm initializing the usrp_std module properly;
I'm not sure of the order of events that should happen to start getting data
out
of the module. I can never get it to assert the usbrdy[1] signal, and thus it
never has data ready . Here are the highlights of what I do:
I create a usb, adc, and master clock: (default time unit is ns)
always #16 clk_120mhz = ~clk_120mhz; //1/16ns = 62.5MHz (?)
always #60 usbclk = ~usbclk; //1/60ns = 16.67MHz (what does FX2 give us?)
always #16 adclk = ~adclk; // 1/16ns = 62.5MHz
I start generating adc data
always @(posedge adclk) adc1_data <= #1 adc1_data + 1;
always @(posedge adclk) adc2_data <= #1 adc2_data + 1;
I (think) I reset the rx and (presumably non-existent) tx chains:
#1000
send_config_word(`FR_MASTER_CTRL,32'hc); //TX, RX reset
I then set up what I think are the pertinent registers to get the rx chains
going:
#1000
send_config_word(`FR_MASTER_CTRL, 32'h2); //RX enable
send_config_word(`FR_RX_SAMPLE_RATE_DIV, 32'h2); // 128e6/64e6 = 2 divisor
(closest!)
send_config_word(`FR_DECIM_RATE, 32'h1); //decimation rate = 1
send_config_word(`FR_RX_FREQ_0, 32'h0); //ddc center freq, rx0 = 0
send_config_word(`FR_RX_FREQ_1, 32'h0); //ddc center freq, rx1 = 0
send_config_word(`FR_RX_PHASE_0, 32'h0); //ddc phase acc word
send_config_word(`FR_RX_PHASE_1, 32'h0); //ddc phase acc word
send_config_word(`FR_RX_MUX, {12'h0, 2'h3, 2'h3, 2'h2, 2'h2, 2'h1, 2'h1, 2'h0,
2'h0, 1'b1, 3'h0});
//rx mux set so that DDCn gets ADCn, complex samples ignored
send_config_word(`FR_RX_FORMAT, {21'h0, 1'b0, 1'b1, 5'hf, 4'h0}); //set rx
data
format control register: 16 bits, want Q
I can see in ModelSim that the serial data is banged in properly. However, I
get no joy. The usrp_std module simply never spits anything out. The
burst_usb_read() task included with the test bench code waits for usbrdy[1] to
be asserted, but it never does. I've already tried to set the OE and RD inputs
to see what happens, but nothing does.
Any input would be greatly appreciated.
Nelson.
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