Hi,
In my work i have generated random sequenece and then done ofdm modulation
on it, further i want to use the maximum of the absolutes of ofdm signal.But
if i look on max block its has two i/p i dont no what its mean coz it should
take one i/p from the absolute values of ofdm . could any suggest
Hi, all
I have read a lot from the mailing list. And I know that we can use the
reference clock to lock the clock on the USRP2, then use the command
config_mimo() and sync_to_pps() to synchronize the USRP2s.
I want to ask that how to use the timestamps to synchronize the data
since the m-block is
Thanks,
i will test it monday on PS3 an will tell my results!
Regards
Matty
2010/4/30 Eric Blossom
> On Fri, Apr 30, 2010 at 09:08:59AM +0200, matty wrote:
> > I want to set up several Benchmark Tests for PowerPC Processors using
> > Altivec.
> > The MP-Scheduler Benchmark works for Core2 Duo
Hi all,
I want use USRP as Active Radar. In first time my aim is to emit a RF
pulse at 64 MHz, and receive echo. For this i have read the comment in
"gnuradio/gr-radar-mono/src/fpga/top/config.vh", the two last lines is:
// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz
//`define TX_RATE_M
On Sat, May 1, 2010 at 05:13, sam wrote:
> I want use USRP as Active Radar. In first time my aim is to emit a RF
> pulse at 64 MHz, and receive echo. For this i have read the comment in
> "gnuradio/gr-radar-mono/src/fpga/top/config.vh", the two last lines is:
>
> // Uncomment to enable 64 MHz Tx
I checked and they're not hundreds. In fact there does not seem to be
anything unusual about that.
Plus I see some 'S' sequences every 3 or 4 failed scans too. In USRP2 usage
FAQ, it says this happens when packets are dropped. But I don't know which
one causes the other one.
Rahman
On Sat, May
Dear all,
USRP2 FPGA can be reprogrammed and u2_rev3.bin will be generated and wrote to
the SD card.
How about reprogramming the CPLD? Any advice on programming CPLD?
Please help.
Thanks
___
On 05/01/2010 04:40 PM, Rahman Doost wrote:
> I checked and they're not hundreds. In fact there does not seem to be
> anything unusual about that.
> Plus I see some 'S' sequences every 3 or 4 failed scans too. In USRP2
> usage FAQ, it says this happens when packets are dropped. But I don't
> know
Yes that's correct. It always works fine at the start.
On Sat, May 1, 2010 at 6:52 PM, Marcus D. Leech wrote:
> On 05/01/2010 04:40 PM, Rahman Doost wrote:
> > I checked and they're not hundreds. In fact there does not seem to be
> > anything unusual about that.
> > Plus I see some 'S' sequences
On 05/01/2010 02:48 PM, utsu nn wrote:
Dear all,
USRP2 FPGA can be reprogrammed and u2_rev3.bin will be generated and
wrote to the SD card.
How about reprogramming the CPLD? Any advice on programming CPLD?
Please help.
Thanks
You will need a JTAG programmer. J203 fits the Xilinx platform
Two Questions:
1) GRC comes with a slider but no command button (like the one with
usrp_probe). Is there an easy way to add one to GRC ?
Do I have to add one afterward using a python editor ??
2) Is there any way to implement a timer event with GRC ? I want
to step the "f
On 05/01/2010 06:48 PM, William Pretty Security Inc wrote:
Two Questions:
1) GRC comes with a slider but no command button (like the one with
usrp_probe). Is there an easy way to add one to GRC ?
The variable chooser implements a button.
Do I have to add one afterward using a pytho
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