On Wednesday 08 March 2006 11:35, Eric Blossom wrote:
> Here are a couple of specific suggestions:
I'll second the suggestions, and add a third for those who want to do FPGA
development:
'Digital Signal Processing with Field Programmable Gate Arrays' 2nd Ed, Uwe
Meye-Baese. Published by Springe
On Wed, Mar 08, 2006 at 08:45:04AM +0100, Matteo Campanella wrote:
> great... this should mean we should be able to test alot of examples
> removing the xlating filter from the chain... I hope to run some tests
> asap; in the meanwhile Eric, what is a good starter example to understand
> how to dec
On Wed, Mar 08, 2006 at 05:42:56PM +0100, Matteo Campanella wrote:
> I also meant a gnuradio example, eg. some block that does this already or
> almost ;-)
> > On Wed, Mar 08, 2006 at 08:45:04AM +0100, Matteo Campanella wrote:
> >> great... this should mean we should be able to test alot of exampl
On Sun, Mar 05, 2006 at 10:32:05PM -0500, David I. Emery wrote:
> On Sun, Mar 05, 2006 at 05:53:44PM -0800, Eric Blossom wrote:
> >
> > In the FPGA, the phase word (not the accumulator) is approximately
> > 15-bits wide. This gives worst case phase-truncation spurs of -90 dBc.
> > This looks smal
On Sun, Mar 05, 2006 at 12:03:33PM -0800, Eric Blossom wrote:
> Good question. I've wanted to revisit it myself too.
> As I recall it was to reduce the spurs in the DDC output.
> If you get a chance, please see if you can find relevant papers.
> I suggest searching for "DDS spurs", or something li
Eric Blossom wrote:
> On Sun, Mar 05, 2006 at 08:12:37AM +0100, Matteo Campanella wrote:
>
>>I digged into the usrp c code, and I have found the following code, that
>>basically says we could use 32 bits for tuning on the fpga, but we truncate
>>it to 14 - unless there's a good reason for that,
On Sun, Mar 05, 2006 at 07:18:40PM -0500, David I. Emery wrote:
> On Sun, Mar 05, 2006 at 12:03:33PM -0800, Eric Blossom wrote:
> > Good question. I've wanted to revisit it myself too.
> > As I recall it was to reduce the spurs in the DDC output.
> > If you get a chance, please see if you can find
On Sun, Mar 05, 2006 at 05:53:44PM -0800, Eric Blossom wrote:
>
> In the FPGA, the phase word (not the accumulator) is approximately
> 15-bits wide. This gives worst case phase-truncation spurs of -90 dBc.
> This looks small enough that we can safely ignore it. Therefore,
> I suggest we stop tru
On Sun, Mar 05, 2006 at 08:12:37AM +0100, Matteo Campanella wrote:
> I digged into the usrp c code, and I have found the following code, that
> basically says we could use 32 bits for tuning on the fpga, but we truncate
> it to 14 - unless there's a good reason for that, we could be much more
>
