On Sun, Mar 05, 2006 at 05:53:44PM -0800, Eric Blossom wrote:
>
> In the FPGA, the phase word (not the accumulator) is approximately
> 15-bits wide. This gives worst case phase-truncation spurs of -90 dBc.
> This looks small enough that we can safely ignore it. Therefore,
> I suggest we stop truncating the tuning word on the host side.
>
> Also, if we stop truncating on the host, then our frequency tuning
> resolution will be 64e6 / 2**31 = 0.03 Hz. Probably fine enough for
> most uses.
I'd certainly suggest that if you decide NOT to support this
high resolution setting as a default, you provide a method for doing
so for applications where best spurious performance is less critical
than the myriad advantages of being able to set the downconverter
right on channel rather than synthesizing that (in a bunch of cycles)
with various errors and resource consumption.
--
Dave Emery N1PRE, [EMAIL PROTECTED] DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."
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