On Fri, Jul 23, 2010 at 12:31:19PM -0700, Ashish Bansal wrote:
> Hi,
> I am trying to understand the data flow in the FPGA. I am trying to
> understand the Architecture and aemb firmware program control flow.
> Which one is the top level firmware "C" file. How it gets data from ADC. How
> it intera
Hi,
I am trying to understand the data flow in the FPGA. I am trying to
understand the Architecture and aemb firmware program control flow.
Which one is the top level firmware "C" file. How it gets data from ADC. How
it interacts with the UART etc.Please let me know some details on it.
Thanks
JS
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