On Mon, Aug 21, 2006 at 07:53:06PM -0700, Oussama Sekkat wrote:
> Eric,
>
> thank you so much. It works nicely now.
> I did what as you suggested: compiled the verilog code on my windows machine
> and transferred it over to my Ubuntu machine. I then made sure to change the
> fpga filename as you s
Eric,thank you so much. It works nicely now.I did what as you suggested: compiled the verilog code on my windows machine and transferred it over to my Ubuntu machine. I then made sure to change the fpga filename as you showed me.
I can now use the debug pins to monitor the signals I want.Thank you
On Mon, Aug 21, 2006 at 12:32:11AM -0700, Oussama Sekkat wrote:
> Thank you very much Eric.
>
> I tried it both ways and it works.
Glad to hear it ;)
> For the second way, I enabled the debug outputs as you showed me. When I
> connect the pins to my logic analyzer, it seems that the 16 bit outpu
Thank you very much Eric.I tried it both ways and it works.For the second way, I enabled the debug outputs as you showed me. When I connect the pins to my logic analyzer, it seems that the 16 bit output is always the same : the only bits asserted were bit 1,2,,4,8. I suppose this is some kind of
On Sat, Aug 19, 2006 at 11:14:33PM -0700, Oussama Sekkat wrote:
> Hi,
> I generated a signal using the usrp_siggen.py function and tried to use the
> IO_pins on the basic TX board to monitor the digital output on a logic
> analyzer but it seems that no signal goes to those pins.
> Is there somehtin
Hi,I generated a signal using the usrp_siggen.py function and tried to use the IO_pins on the basic TX board to monitor the digital output on a logic analyzer but it seems that no signal goes to those pins. Is there somehting I need to change in the verilog code to be able to use the debug IO pins?
