I generated a signal using the usrp_siggen.py function and tried to use the IO_pins on the basic TX board to monitor the digital output on a logic analyzer but it seems that no signal goes to those pins.
Is there somehting I need to change in the verilog code to be able to use the debug IO pins?
Any suggestions on how to observe the output on a logic analyzer?
Thank you,
Oussama.
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