Hi All,
As you can read previous posts on this thread and can know from that I am
trying to detect the cycle time of a cyclic data transmitter by sensing the
channel.
>From discussion on this thread I understood in the following way:
USRP RF sampling rateAfter decimation with D=256---S
On Mon, Mar 23, 2009 at 08:00:52AM -0700, kaleem ahmad wrote:
>
> Hi,
>
> I have one more confusion about this sampling rate of USRP.
>
> At FPGA level it is 64MSps and when we decimate (D = 4...256), the sampling
> rate is reduced to 64MSps/D. Now I am confused that if the actual sampling
> ra
On Mon, Mar 23, 2009 at 11:04 AM, kaleem ahmad wrote:
>
> Thanks Brian,
>
> By cycle time I mean that a transmitter (e.g. FSK, ZigBee or any other) is
> transmitting something (I am not interested what is being transmitted) after
> fixed time intervals let say 50ms. Now this transmitter will conti
Thanks Brian,
By cycle time I mean that a transmitter (e.g. FSK, ZigBee or any other) is
transmitting something (I am not interested what is being transmitted) after
fixed time intervals let say 50ms. Now this transmitter will continue
transmitting data after every 50ms. This 50ms is the cycle ti
Hi,
I have one more confusion about this sampling rate of USRP.
At FPGA level it is 64MSps and when we decimate (D = 4...256), the sampling
rate is reduced to 64MSps/D. Now I am confused that if the actual sampling
rate of USRP is changed from 64MSps to the new decimated sampling rate or
the US
On Mon, Mar 23, 2009 at 10:20 AM, kaleem ahmad wrote:
>
> Thanks for all these replies,
>
> The problem is my investigation about cycle time is not restricted to FSK,
> I just gave the example of FSK system. I would like to calculate the cycle
> time of any system (ZigBee, FSK, CSS etc) present i
Thanks for all these replies,
The problem is my investigation about cycle time is not restricted to FSK,
I just gave the example of FSK system. I would like to calculate the cycle
time of any system (ZigBee, FSK, CSS etc) present in the area. My target is
to sense as much systems as possible and
kaleem ahmad wrote:
Thanks Ed,
ADC sampling rate = 64MHz
it gives resulution time = 1/64MHz = 156 ns
if we choose N=512 for FFT then total observation time for one scan(one
complete FFT) is = 156ns x 512 = 8 micro sec
if the maximum possible (expected) cycle time is 200ms then:
it needs 200ms/
Hi,
> On Fri, 3/20/09, kaleem ahmad wrote:
>
> ADC sampling rate = 64MHz
> it gives resulution time = 1/64MHz = 156 ns
> if we choose N=512 for FFT then total observation time for
> one scan(one
> complete FFT) is = 156ns x 512 = 8 micro sec
> if the maximum possible (expected) cycle time is 20
On Fri, Mar 20, 2009 at 10:33 AM, Brian Padalino wrote:
> Assuming an FSK system with unknown frequency separation and baudrate,
> is the above algorithm robust enough to determine said parameters to
> then pass along to a coherent demodulator to achieve a better BER?
Yes, though perhaps not in
On Fri, Mar 20, 2009 at 1:27 PM, Johnathan Corgan
wrote:
> A common, non-coherent method for FSK demodulation and baud rate
> detection is to multiply each succeeding sample by the complex
> conjugate of the preceding sample, then take the phase of the product.
> This turns the sample series into
On Fri, Mar 20, 2009 at 10:11 AM, Brian Padalino wrote:
> FSK is all about delta phase shifts. If a mark is a + frequency, and
> a space is a - frequency (or vice versa, your choice), then I would
> think it would be easy to keep track of how large the deltas between
> phases were and when they
On Fri, Mar 20, 2009 at 11:30 AM, kaleem ahmad wrote:
>
> Thank Brian,
>
> Can you give some hint, what do mean ??? I mean a little idea what do you
> want to say?
FSK is all about delta phase shifts. If a mark is a + frequency, and
a space is a - frequency (or vice versa, your choice), then I
Thank Brian,
Can you give some hint, what do mean ??? I mean a little idea what do you
want to say?
Best Regards
Brian Padalino wrote:
>
> On Fri, Mar 20, 2009 at 9:34 AM, kaleem ahmad
> wrote:
>>
>> Thanks Ed,
>>
>> ADC sampling rate = 64MHz
>> it gives resulution time = 1/64MHz = 156 ns
>
On Fri, Mar 20, 2009 at 9:34 AM, kaleem ahmad wrote:
>
> Thanks Ed,
>
> ADC sampling rate = 64MHz
> it gives resulution time = 1/64MHz = 156 ns
> if we choose N=512 for FFT then total observation time for one scan(one
> complete FFT) is = 156ns x 512 = 8 micro sec
> if the maximum possible (expect
Thanks Ed,
ADC sampling rate = 64MHz
it gives resulution time = 1/64MHz = 156 ns
if we choose N=512 for FFT then total observation time for one scan(one
complete FFT) is = 156ns x 512 = 8 micro sec
if the maximum possible (expected) cycle time is 200ms then:
it needs 200ms/8microsec = 2500 contin
kaleem ahmad wrote:
3- Can you suggest some different way to solve this problem, The problem is
simply to calculate the cycle time of some system which is already working
in the environment
Since your unknown FSK signal has a regular cycle time, it should be
relatively easy to detect. Fo
Hello every one,
I am using USRP1 with RFX2400 daughter card.
I have a system (any state of the art system, let say Atmel's narroband FSK
which works in 2.4 GHz band) transmitting a fixed packet cyclically (let say
cycle time = T ms).
I want to use USRP system to sense the spectrum and calcu
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