Hi,

> On Fri, 3/20/09, kaleem ahmad <kaleem_...@yahoo.com> wrote:
> 
> ADC sampling rate = 64MHz
> it gives resulution time = 1/64MHz = 156 ns
> if we choose N=512 for FFT then total observation time for
> one scan(one
> complete FFT) is = 156ns x 512 = 8 micro sec
> if the maximum possible (expected) cycle time is 200ms
> then:
> it needs 200ms/8microsec = 2500 continues FFT scans to
> cover the range of
> frequencies that correspond to 200ms cycle time.
> 
> Is above calculation correct?
> 


The above calculation is only true at FPGA level (ADC=64MHz). At PC side, max 
sampling is 8MHz (125nsec). So acquisition time for 512 FFT is 64 usec. 

If the frequency is constant, you can use DFT instead of FFT.

Best Regards,

Firas


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