>> There is a configurable scale factor (see the stream args in the grc
>> block). It defaults to a value that gives you the upper 8.
>>
>> -Josh
>>
> I noticed there was a "scalar=1024" option. Is that just a multiplier
> that UHD applies on the host
> side for 8-bit samples, or does it affect
My AMD Athlon(tm) II X4 620 Processor does jyst fine with 50Msps FFT
plotter. Just sayin :-)
Hmmm, is the Athlon II generally better than the Phenom II (insns/clock?
). I suppose I should try it on my
1090T as well, which is rather faster than the 1055T I tried it on
tonight. But that mean
On 11/09/2011 07:07 PM, Marcus D. Leech wrote:
> Just did a quick test of 8-bit samples on a USRP2, on one of my 6-core
> AMD machines.
>
> I can get to 33Msps with a fairly simple SOURCE-->MULT-->FFT_SINK
> flow-graph, but anything more complicated causes overruns.
>
> If I try 50Msps, I get n
Just did a quick test of 8-bit samples on a USRP2, on one of my 6-core
AMD machines.
I can get to 33Msps with a fairly simple SOURCE-->MULT-->FFT_SINK
flow-graph, but anything more complicated causes overruns.
If I try 50Msps, I get near-continuous overruns.
This is on an AMD Phenom II X6-10
Hello,
I have looked everywhere, including through the Verilog FPGA code and in
the Python scripts, but nowhere can I find how to use 8-bit samples.
According to usrp_fft.py, the -8 and --no-hb options should allow a
decimation factor of 4, but nothing I can do will return anything but
zeroe
Matt Ettus wrote:
Look at the samples in the scope sink. Do you see a pattern of A A B B
C C D D, meaning instead of unique samples, is every one repeated?
If so, it means that the halfband decimator is probably not being
bypassed properly.
Here are the first 100 8 bit samples from the
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On Jul 11, 2008, at 11:24 AM, Chris Stankevitz wrote:
Matt Ettus wrote:
Remember that while the ADCs are 12 bits, we carry 16+ bits of
precision throughout the signal processing.
How do you get 16 bits of precision from a 12 bit ADC? What does
Matt Ettus wrote:
Remember that while the ADCs are 12 bits, we carry 16+
bits of precision throughout the signal processing.
Matt,
How do you get 16 bits of precision from a 12 bit ADC? What does 16+
mean? I'm looking at the shorts coming from the USRP and I'm seeing
values in the range
Chris Stankevitz wrote:
Johnathan Corgan wrote:
You *may* be seeing an artifact of the truncation of the ADC samples.
Johnathan, others:
I believe this is not the case. When I download 16 bit samples from
the USRP and remove the 4LSBs myself, the spectrum looks normal. When
I ask the US
Chris Stankevitz wrote:
Johnathan Corgan wrote:
You *may* be seeing an artifact of the truncation of the ADC samples.
Johnathan, others:
I believe this is not the case. When I download 16 bit samples from
the USRP and remove the 4LSBs myself, the spectrum looks normal. When
I ask the US
Johnathan Corgan wrote:
You *may* be seeing an artifact of the truncation of the ADC samples.
Johnathan, others:
I believe this is not the case. When I download 16 bit samples from the
USRP and remove the 4LSBs myself, the spectrum looks normal. When I ask
the USRP for 8 bit samples, the
Johnathan Corgan wrote:
You *may* be seeing an artifact of the truncation of the ADC samples.
Johnathan:
Thank you, that's exactly what it looks like. Adding USRP pga gain
didn't help though. I'll get back to the group...
Chris
___
Discuss-gnu
On Thu, Jul 10, 2008 at 10:39 PM, Chris Stankevitz
<[EMAIL PROTECTED]> wrote:
> 1. Why does b) show a lobe while a) does not?
> 2. Why do b) and c) show lobes at the same pixels (vs shifted .5 MHz)?
You *may* be seeing an artifact of the truncation of the ADC samples.
In 8-bit mode, only the uppe
Hello,
a) Here is a screenshot of 16 bit noise @ 12 MHz:
http://img224.imageshack.us/img224/8981/16bitsb0.png
b) Here is a screenshot of the same noise with 8 bit samples:
http://img60.imageshack.us/img60/5852/8bitqg7.png
c) 8 bit noise, tuned to 12.5 MHz
http://img224.imageshack.us/img224/1596
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