Hello,
I have looked everywhere, including through the Verilog FPGA code and in
the Python scripts, but nowhere can I find how to use 8-bit samples.
According to usrp_fft.py, the -8 and --no-hb options should allow a
decimation factor of 4, but nothing I can do will return anything but
zeroes. It has been mentioned in other discussions on this list that
this was working in the past, so what gives? Getting very frustrated here!
~Jeff
--
~Jeffrey Lambert, K1VZX
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