I see. Thanks.Also, I was looking at the serial_io.v module but I am not sure what its purpose is or what it does.If I am not mistaken, it reads the data from the Cypress USB controller chip. What does it do to that data?
Oussama.On 7/12/06, Matt Ettus <[EMAIL PROTECTED]> wrote:
Oussama Sekkat wrot
Oussama Sekkat wrote:
Hi,
Thanks for your reply.
So from what I understand, in the transmit side the digital up
converters are implemented in the AD9862 chip but the interpolation is
done in the FPGA.
On the transmit side we use our own CIC to interpolate from whatever
ratio comes over the
Hi,
Thanks for your reply.
So from what I understand, in the transmit side the digital up
converters are implemented in the AD9862 chip but the interpolation is
done in the FPGA. I believe in the receive side the down conversion is done in the FPGA. So why can't we do the same for the transmit sid
On Mon, Jul 10, 2006 at 08:22:29PM -0700, Oussama Sekkat wrote:
> Hello everybody,
>
> I am still a beginner in the project so bare with me if my questions have
> obvious answers.
> I was looking at the verilog code for usrp_std.v module. that module
> containes the tx_chain.v module which uses a
Hello everybody,I am still a beginner in the project so bare with me if my questions have obvious answers.I
was looking at the verilog code for usrp_std.v module. that module
containes the tx_chain.v module which uses a module called phase_acc. I
am not sure what this later module does? It takes as
