I am still a beginner in the project so bare with me if my questions have obvious answers.
I was looking at the verilog code for usrp_std.v module. that module containes the tx_chain.v module which uses a module called phase_acc. I am not sure what this later module does? It takes as inputs (among others) a 7bit serial address and 32 bit serial data and outputs the 32bit phase.
Does anyone have any idea what that module does and what its purpose is in the tx_chain?
Thank you,
Oussama.
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