Thanks a lot for the feedback. I got it to work eventually.
Eric Blossom wrote:
On Tue, Apr 14, 2009 at 04:03:13AM -0700, karim wrote:
Eric Blossom wrote:
On Thu, Apr 09, 2009 at 09:46:43AM -0700, karim wrote:
Hi,
I am trying to use the dqpsk modulator block to modulate some data
and
Eric Blossom wrote:
On Thu, Apr 09, 2009 at 09:46:43AM -0700, karim wrote:
Hi,
I am trying to use the dqpsk modulator block to modulate some data and
then take the output and separate it to real and imag. This is the code,
it runs but the sinks are empty and have no data. What am I doing
t does it mean?
My code is below.
Cheers,
Karim
#no GUI
#source: stream from file_source
#connect with DQPSK: input: byte stream, output:complex
#change it to 2 parts:imagine and Real
#connect with gr.complex_to_real or gr.complex_to_imag
#display data in sink1 (real) and sink2 (imag)
class my_
Thanks a lot Eric.
That's very useful. Yes, you are right about the preamble.
At this stage I am just doing the transmitter, later I will worry about
how to correctly receive it and will probably add a preamble.
Ed Criscuolo wrote:
karim wrote:
Hi,
I need to implement a simple transm
Jason Uher wrote:
I checked the benchmark_tx.py it adds a preamble and a lot of data before
the actual payload which I don't need.
I assume you are trying to do some BER measurements? There is an
example called digital-bert that will do that (bert=bit error rate
tester).
Actually I am not
and a lot of data
before the actual payload which I don't need.
Thanks
Karim
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;s good to know.
Eric Blossom wrote:
On Tue, Mar 10, 2009 at 05:33:36AM +0100, Karim El Defrawy wrote:
Hi,
I am using a FLEX2400 transceiver daughterboard and was wondering what's
the minimum step size that I can use to set the center frequency.
I tried steps down to 500KHz a
tried lower steps I was not able to see any difference in the
generated frequency.
Thanks,
Karim
Sebastiaan Heunis wrote:
Hi
Can anyone please suggest a setup that I can use to test the maximum
value of samples? I know that we have 16bit signed values. Looking
at the ADC interface on the
s pni monitor ds_cpl vmx est tm2 ssse3
cx16 xtpr lahf_lm ida
bogomips: 4388.83
clflush size: 64
Cheers,
Karim
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