[Discuss-gnuradio] Problem with the FPGA firmware (getting clock like output only)

2007-08-19 Thread eenrti
Hello list, I have recently changed the USRP clock with an external PLL. Then I used the previously precompiled standard firmware std_4rx_0tx.rbf , using 2 sinusoidal inputs to RXA, RXB and it was confirmed that everything was working fine. I then downloaded the 3.0.4 version and tried to recom

[Discuss-gnuradio] 4-bit quantization and rounding

2007-07-31 Thread eenrti
Hello I have built a lower-bit quantization scheme in the rx_bufffer.v using 4-bit samples, storing one byte for each clock sample (for both I and Q) and then filling up the 16-bit FIFO with another 8 bit value coming from the next clock sample. Whan I did some tests and plotted the results e

[Discuss-gnuradio] Reducing the bits per sample

2007-07-11 Thread eenrti
Hello, I am posting this again since I did not get a reply, I am sorry if I should not but I would really like to get some help. one task of the project I have been working on is to collect raw 4-bit samples from two input to a basic RX daughterboard (RXA, RXB) connected to two IF signals. W

[Discuss-gnuradio] Reducing resolution and packing samples in FPGA firmware problem

2007-07-05 Thread eenrti
Hello, one task of the project I have been working on is to collect raw 4-bit samples from two input to a basic RX daughterboard (RXA, RXB) connected to two IF signals. We have been working on reducing the number of bits per sample taken from within the rx_buffer.v file. In that file we are c

[Discuss-gnuradio] Asking info about the Interleaving of samples

2007-03-29 Thread eenrti
Hello, I have used a sinusoidal signal generator to test my USRP output stream using a single or even the teo inputs to the RX daughterboard. I suppose there are 4 channels at the end when I use both RX daughterboard inputs, for I and Q so I tried to separate my output data by using a 4 sample

[Discuss-gnuradio] Intrerleave output from usrp_rx_cfile.py

2007-03-29 Thread eenrti
Hello, I have used a sinusoidal signal generator to test my USRP output stream using a single or even the teo inputs to the RX daughterboard. I suppose there are 4 channels at the end when I use both RX daughterboard inputs, for I and Q so I tried to separate my output data by using a 4 sample

[Discuss-gnuradio] Sampling rate of USRP board

2007-03-26 Thread eenrti
Hello, I have recently purchased the USRP board and the RX daughterboard, and I have started working on them. One major factor that I need to change is the sampling rate frequency of the ADCs on USRP, I know the USRP clock is at 64MSPS and I need to reduce it to at least half of it. My question

[Discuss-gnuradio] Hello all (asking for some help)

2007-02-01 Thread eenrti
I know it will sound strange since for the last day that I have been subscribed to this list I can see many advanced (at least to me) topics but I am new to it, I have just purchased the USRP motherboard and I have many many questions. To start with the more simple ones, I would like to ask wha