Sorry to resurrect this somewhat old thread, but I'm mightily confused by
something. Mike originally said:
"For my simple setup I've got 2 N210's each with an RFX2400 (using TX/RX for
receive)."
The Ettus website says:
"The user may set the receive antenna to be TX/RX or RX2. However, when
usin
> For my simple setup I've got 2 N210's each with an RFX2400 (using TX/RX for
> receive).
>
Are you sure you're really using TX/RX for receive? As the link Josh
supplied says "The user may set the receive antenna to be TX/RX or RX2.
However, when using an RFX board in full-duplex mode, the receiv
> Although we haven't come across any projects with USRP1 for successful
> testing for STBC and SFBC codes.
> If any team or individual has published this work, we would be happy to
> check that part.
>
The Hydra project (http://netlab.ece.utexas.edu/hydra/) has space-time block
codes as defined i
Hi all,
Although there are methods for supplying +5V to a receive antenna on the
DBSRX daughterboards, I just wanted a final sanity check to verify that
there is not something similar for the RFX (in particular 1800)
daughterboards before I go and buy an external bias tee.
I've looked in the arch
Hi Phil,
I realize this isn't the GPS-SDR mailing list but this should be
documented somewhere. From what I can tell, it looks like in one of
his more recent commits, Mr. Heckler did a search and replace, from
printf(
to
fprintf(stdout,
He did this to clear up some bug he was getting. Howeve
I've made a few small changes to the inband FPGA code to allow for
interleaving of channels, which is necessary for our application.
I've gotten it to compile and have done some live testing on the USRP,
and it seems to be working. I have, however, had an extremely
frustrating time trying to simul
> The current inband RX chain looks like:
>
>N RX Sample Streams -> N RX Sample FIFOs -> 1 Packet Builder -> 1
> USB FIFO -> FX2 USB Interface
>
> What it should look like (in my opinion):
>
>N RX Sample Streams -> N Packet Builders -> N Packet FIFOs -> N:1
> FIFO MUX -> FX2 USB Interface
> As a non-hardware person, I was thinking that a simple solution is to not
> really use the clock on the RX directly, but timestamp packets indirectly.
> You have a signal when the sample buffer is empty, when that signal is
> de-asserted for the first time, read the clock and take this as your i
Hi again George,
> I spend all of my time working with the single chain, and if I find bugs I
> can fix them. But I think you're the only ones using the dual chain... so
> your feedback is useful and I'd appreciate any help solving the problems. I
> don't really know Verilog, and our Verilog cod
> Ketan Mandke wrote:
>>
>> George,
>>
>> I am sure that Steve will check the single rx-chain and get back to
>> you with the results of that test.
>>
>> Although, I have a hypothesis about what might be happening. Is it
>> possible that there are some control signals being sent to the USRP
>> over
Hi George,
Thanks for the quick and thought-out response. I actually tried with
the new rbf yesterday. It produces no noticeable differences in the
output I'm interested in at this point.
Second, we are not seeing any underrun. I have verified this in two
ways. First, I check pkt->underrun()
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