Hi Stefan,
I was trying to install your module from source code but received following
errors while doing make:
gr_convolution_dec.lo -MD -MP -MF .deps/gr_convolution_dec.Tpo -c
gr_convolution_dec.cc -fPIC -DPIC -o .libs/gr_convolution_dec.o
gr_convolution_dec.cc:405:2: warning: no newline at e
On Wed, Mar 21, 2007 at 05:31:36PM -0400, [EMAIL PROTECTED] wrote:
> Thanks again for the help. I think I better understand how to set
> the RX mux. I am now working on the multi_file.py example to
> receive using 2 daughterboards on the same USRP. I want to do the
> same type of thing using 2
Hi all
I know that could be a silly question , but i wanna make sure ,
What are the range of IF frequency .
Thanks in advance
Ayman
-
The best gets better. See why everyone is raving about the All-new Yahoo! Mail.
_
One you may not have considered is Apple's Macbook Pro.
You can keep Mac OS X or dual boot to Linux.
USB performance is good but the MBP also has Firewire
so you can attach a huge RAID if you want and get quite
a lot of disk bandwidth without taking any from USB.
Mac OS X has some interesting f
Thanks again for the help. I think I better understand how to set the RX mux.
I am now working on the multi_file.py example to receive using 2 daughterboards
on the same USRP. I want to do the same type of thing using 2 antennas where
RX-A and RX-B (on side A) will receive signal 1's I and Q
On 3/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
So, if I have correctly understood, I would use dual_clock ram component
(altsyncram for instance) and only pass the packet address (and maybe
its length) to the next block. If the whole packet (including padding)
is stored in the RAM then
Using your perfect samples (the ones you get with decim=8), can you
try low pass filtering them (without decimating) to the equivalent
width that you'd get with the decim=256 setting, and then plotting
them?
Maybe it's not perfectly round because with the narrower filter, we're
losing more of th
So, if I have correctly understood, I would use dual_clock ram component
(altsyncram for instance) and only pass the packet address (and maybe
its length) to the next block. If the whole packet (including padding)
is stored in the RAM then it's easy because all my memory block are the
same size
On Wed, Mar 21, 2007 at 10:05:03AM -0700, Chris Stankevitz wrote:
>
> steve wrote:
> >Hi,
> >
> >is it possible to change the frequency/band of the USRP from within
> >a gr block?
>
>
> Is it possible to write a python-only block (without c++)?
>
> If so, your c++ block could feed an output sig
On Tue, Mar 20, 2007 at 08:07:04PM -0400, Brian Padalino wrote:
> The length of the packet is built into the packet, isn't it? Do we
> need to keep a count of the packet length, or just take it from the
> packet itself?
>
> Brian
The payload length is in the packet. The total length including t
On Wed, Mar 21, 2007 at 12:52:30PM -0400, Brian Padalino wrote:
> On 3/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
> >How do the fpga know is data is interleaved or not ?
>
> I believe all samples sent down is interleaved over USB to 16-bit I
> followed by 16-bit Q samples.
See below for
On Wed, Mar 21, 2007 at 12:45:00PM -0400, Thibaud Hottelier wrote:
> How do the fpga know is data is interleaved or not ?
>
> I am still worried about the number of fifo that will be used and their
> size. The FPGA looks pretty full. Is there a way to have a memory
> separated from the FPGA that
On Wed, Mar 21, 2007 at 10:08:50AM +, steve wrote:
> Hi,
>
> is it possible to change the frequency/band of the USRP from within
> a gr block?
>
> What's the latency? I'm thinking about (slow) frequency hopping in GSM.
>
> My gr block is started from a python script 'run.py'. Is it possible
steve wrote:
Hi,
is it possible to change the frequency/band of the USRP from within
a gr block?
Is it possible to write a python-only block (without c++)?
If so, your c++ block could feed an output signal "what frequency to
tune" to the python-only block which would tune the USRP.
Chri
On 3/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
How do the fpga know is data is interleaved or not ?
I believe all samples sent down is interleaved over USB to 16-bit I
followed by 16-bit Q samples. These can be concatenated (since they
are of the same sample time) to 1 32-bit number
How do the fpga know is data is interleaved or not ?
I am still worried about the number of fifo that will be used and their
size. The FPGA looks pretty full. Is there a way to have a memory
separated from the FPGA that I could access through a bus?
Thibaud
Brian Padalino wrote:
Something e
Probably won't come as a surprise to those who know me, but we have
used MacBook Pro's with good results. While I've never tried, in
theory a MacBook (not Pro) could also suffice, since internally it's
about the same as the Intel iMac, of which we also have a number
running GNU Radio at fu
It would be good to see benchmarks of the blocks that dominate
receivers on various processors. I think for our 802.11 receiver the
most time went to FIR filters.
You didn't specify if your workload was floating point or integer; I
suspect that the chip with best performance will be different.
Hi,
is it possible to change the frequency/band of the USRP from within
a gr block?
What's the latency? I'm thinking about (slow) frequency hopping in GSM.
My gr block is started from a python script 'run.py'. Is it possible to
call a function within run.py from my C++ gr block?
thanks,
steve
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