On 3/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
How do the fpga know is data is interleaved or not ?
I believe all samples sent down is interleaved over USB to 16-bit I followed by 16-bit Q samples. These can be concatenated (since they are of the same sample time) to 1 32-bit number to store within a block ram within the FPGA. Doing real-only transmissions could possibly be a status bit to say what the data format is?
I am still worried about the number of fifo that will be used and their size. The FPGA looks pretty full. Is there a way to have a memory separated from the FPGA that I could access through a bus?
We'll be removing one of the RX channels I believe, which frees up a multiplier and a whole boatload of memory. Moreover, the Cyclone has special hard memory blocks that are 4096 bits of dual-port memory. That gives us 128 locations for complex sample storage in a single block. If more blocks are used (which are available), you just double the number every time. It's a lot of FIFOs, but if they are necessary then you have to use them. It's a trade off that you should be aware of, but is also easily checked. Download Quartus II from altera.com and compile the design for the target FPGA. Disable the other RX channel and re-compile to see the change in resources. What do you think?
Thibaud
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