Vincenzo,
I did some experiments with DAB which is, (due to differential
modulation), simpler than DVB. On the PHY level I managed to get
"almost" (about 60%) real-time performance on my P4 with GNU Radio
and prerecorded samples.
This was only PHY (even without channel coding!), and the
synchroni
Hi Eric,
I just saw your cool gnuradio presentation and heard you talking about a not
yet realtime ATSC transmitter.
I am a telecommunication engineering student in italy at Pisa University
(Italy) at the moment, and it is quite likely that my final thesis (to be
started in about a year from now)
Eric Blossom wrote:
The "short" version doesn't touch the data. You'll be able to unpack
it youself.
Strange, I had some problem with rx_cfile not seeming to respect
the width parameter. I'll try it again.
That determines the minimum decimation rate required upstream
from the halfband (4
On Sun, Mar 04, 2007 at 05:51:34PM -0500, [EMAIL PROTECTED] wrote:
> Thanks for the reply. I'm pretty new to GNU radio so I'm still not
> sure exactly what I need to do (I don't know about the whole "which"
> constructor thing). All I've been able to do so far is run the
> examples and modify th
On Monday 05 March 2007 11:26, Brian Padalino wrote:
> I don't think you need anything PCI with the specified PLX chip.
>
> The PEX8311 has a description of:
>
> "8/16/32-bit, 66MHz, Local Bus to PCI Express Bridge"
Whoops you are right.
Weird I haven't seen that before on their site, maybe I'
On 3/4/07, Daniel O'Connor <[EMAIL PROTECTED]> wrote:
You would still need a PCI core although you can get those a lot cheaper than
PCIe cores. You can even get a free one from OpenCores (there is a PCI to
wishbone bridge for example).
I don't think you need anything PCI with the specified PLX
The v4 USRP has a fan header next to the power jack. I don't know what
the recommended solution for v3 USRPs is, although I suspect it's along
the lines you mentioned. :-) Some v3 USRPs already have a power lead
takeoff for an oscillator sub-board on the bottom of the USRP; I suspect
the fan leads
Hello,
Tuesday I am heading off to the biggest pencil in the world for the
Winter SWL Fest in Kulpsville. I am going to do some informal demos of
the USRP and GNURadio. They have a digital radio table in an exhibit
room where they demo DRM. This year they want to do some demos of HD
Radio and I
Weber, Michael J. (US SSA) wrote:
> Eric, I also recently received some enclosures... this is my two cents,
> YMMV, etc:
>
> If the fan is installed such that it blows in onto the USRP, it will
> receive the direct benefit of the airflow. However, the fan makes a lot
> of noise in this configurati
On Monday 05 March 2007 07:44, Brian Padalino wrote:
> With regards to the PCIe interface, were you looking more at just
> getting a PHY transceiver and putting the MAC and other layers in the
> FPGA, or were you more interested in having a PCIe bridge chip that
> handles all of that for you?
>
> I
On Sun, Mar 04, 2007 at 06:20:07PM -0500, [EMAIL PROTECTED] wrote:
> I want to do constellation mapping in pyhton. I have code that does
> a gr.packed_to_unpacked_bb and then gr.chunks_to_symbols_bc using a
> constellation of:
>
> constellation=array((1+1j,1-1j,-1-1j,-1+1j),Complex)
Use this:
I want to do constellation mapping in pyhton. I have code that does a
gr.packed_to_unpacked_bb and then gr.chunks_to_symbols_bc using a constellation
of:
constellation=array((1+1j,1-1j,-1-1j,-1+1j),Complex)
My understanding is that this is the constellation mapping for QPSK. I want to
do con
The ADCs I've been looking at can apparently somehow sample
frequencies above their sampling rate aswell. I'm not really sure how
this works, but I don't think it's an issue I must bother with right
now. Added value for later, I think. Right now I'm only interested in
shortwave transmissions, bu
Thanks for the reply. I'm pretty new to GNU radio so I'm still not sure
exactly what I need to do (I don't know about the whole "which" constructor
thing). All I've been able to do so far is run the examples and modify them as
needed (minor changes). I don't need to know which board is which
On 3/4/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
Oh yes! Sorry, forgot to mention that part.
I'd like to have an ADC with 65 to 105 Msps at 16 bits. This should
allow me to sample up to 30 or 50MHz respectively. I was inspired to
this from the Mercury project of the HPSDR, but that project
On 3/4/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
The Xilinx Virtex-5 LXT's and SXT's have (or will have) hard PCIe
endpoint blocks. This puts most of endpoint IP into dedicated silicon.
slicesDSP48 blocks 10/100/1000Rocket IO
550 MHz
On 3/4/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
It's a very nice chip, but it appears to be very expensive at $38... =(
TI's costs $7, which is quite affordable.
You get a lot for not a lot of money in comparison to writing and
validating your own Transaction and Data Link layers for a
On 3/4/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
On Sun, Mar 04, 2007 at 10:16:21PM +0200, [EMAIL PROTECTED] wrote:
> On 3/4/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
> >>
> >> Hm. Looks like I got my mailing lists crossed. This was intended for
> >> the Open Graphics list, but at least you k
On Mon, Mar 05, 2007 at 12:01:18AM +0200, [EMAIL PROTECTED] wrote:
> On 3/4/07, Brian Padalino <[EMAIL PROTECTED]> wrote:
> >With regards to the PCIe interface, were you looking more at just
> >getting a PHY transceiver and putting the MAC and other layers in the
> >FPGA, or were you more intereste
On Sun, Mar 04, 2007 at 04:14:33PM -0500, Brian Padalino wrote:
> With regards to the PCIe interface, were you looking more at just
> getting a PHY transceiver and putting the MAC and other layers in the
> FPGA, or were you more interested in having a PCIe bridge chip that
> handles all of that for
On 3/4/07, Brian Padalino <[EMAIL PROTECTED]> wrote:
With regards to the PCIe interface, were you looking more at just
getting a PHY transceiver and putting the MAC and other layers in the
FPGA, or were you more interested in having a PCIe bridge chip that
handles all of that for you?
I know Phi
With regards to the PCIe interface, were you looking more at just
getting a PHY transceiver and putting the MAC and other layers in the
FPGA, or were you more interested in having a PCIe bridge chip that
handles all of that for you?
I know Philips and TI have PCIe transceivers which work with Xil
Hi!
I am designing a block, owning an inner object, and now both will need a
communication way. Since it's just one way, your buffer fulfills all my
need.
Do you think I should use a synchronisation object (e.g. mutex)?
The inner object could possibly have an own event processing loop, i.e. can
On Sun, Mar 04, 2007 at 08:44:59PM +0200, [EMAIL PROTECTED] wrote:
> On 3/4/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> >Hello,
> >
> >I'm trying to create a low-cost (below $100€) Software Defined
> >Radio/Spectrum Analyser/Oscilloscope using a high-speed AD converter,
> >an FPGA, and the P
On 3/4/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
Hello,
I'm trying to create a low-cost (below $100€) Software Defined
Radio/Spectrum Analyser/Oscilloscope using a high-speed AD converter,
an FPGA, and the PCIe bus. It would be Open Hardware and compatible
with the efforts of the GNU Radi
Hello,
I'm trying to create a low-cost (below $100€) Software Defined
Radio/Spectrum Analyser/Oscilloscope using a high-speed AD converter,
an FPGA, and the PCIe bus. It would be Open Hardware and compatible
with the efforts of the GNU Radio group.
I don't have a lot of experience with this sort
On Sun, Mar 04, 2007 at 01:33:08AM -0800, Peter Monta wrote:
> Eric Blossom wrote:
>
> >
> >I think that you're really going to want a configurable barrel
> >shifter -- to get the bits where you want them -- then pick them off with
> >round_X or round_X_nearest_even.
> >
>
> OK, the attached rx
Eric, I also recently received some enclosures... this is my two cents,
YMMV, etc:
If the fan is installed such that it blows in onto the USRP, it will
receive the direct benefit of the airflow. However, the fan makes a lot
of noise in this configuration because the blades are right next to the
pe
Hi Eric,
I am designing a matlab guide interface to run the tunnel example and if the
log option is selected, I am planning to throw up another GUI with the plots
of the logged data.
My question at this point is, what kind of plots can be made out of the data
captured. Just to get a feel, I trie
Il giorno dom, 04/03/2007 alle 01.33 -0800, Peter Monta ha scritto:
> Please let me know if anything else is needed for the patch.
> There's a testbench for bit_pack.v I can send along if you like.
Great! I'll try this patch tomorrow. Can you send me the testbench. I
need a testbench for rx_buffe
Eric Blossom wrote:
I think that you're really going to want a configurable barrel
shifter -- to get the bits where you want them -- then pick them off with
round_X or round_X_nearest_even.
OK, the attached rx_buffer.v includes a barrel shifter in bit_pack.v;
I see this was anticipated wit
31 matches
Mail list logo
