Hi,I generated a signal using the usrp_siggen.py function and tried to use the IO_pins on the basic TX board to monitor the digital output on a logic analyzer but it seems that no signal goes to those pins. Is there somehting I need to change in the verilog code to be able to use the debug IO pins?
On Sun, Aug 20, 2006 at 12:24:50AM +0200, Josh Jennings wrote:
> >No just add 'intelToHost_XX()' or 'HostToIntel' functions for reading
> >data, or writing data.
> >Then a host sensitive reader would have these defined appropriately for
> >the endianness of
> >the host.
>
> This is definitely the
No just add 'intelToHost_XX()' or 'HostToIntel' functions for reading
data, or writing data.
Then a host sensitive reader would have these defined appropriately for
the endianness of
the host.
This is definitely the way to go. I have written the intel_to_host
functionality. I will do as Eric pr
On Fri, Aug 18, 2006 at 03:02:31PM -0400, Michael Dickens wrote:
> I just submitted a ticket (41) for this one. Sorry about the bad
> formatting in the ticket ... I'll do better next time.
No problem.
Just use
{{{
around verbatim sections
like this...
}}}
On Aug 9, 2006, at 7:23 PM, Eric Blossom wrote:
Please note that CVS/SVN is not longer the latest code.
We've moved to an integrated Trac + SVN repository.
[I'll delete the old CVS repo real soon now]
Hello,
I even tried the new repository with same results. I checked
usrp_dbid.py for th
On Fri, Aug 18, 2006 at 11:02:59PM -0700, Oussama Sekkat wrote:
> Hello,
>
> When the USRP is plugged in, the LED to the right of the USB controller
> blinks at a fast rate of about 3 times per second. Once a USRP application
> starts, that rate slows down to about 1 time per second. What controls
