Can I ask if there is a beginners list for electronics?
I need to know the subject of Hispeed A/D bit deep
and esentials.
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On Fri, Nov 11, 2005 at 12:09:13PM -0500, [EMAIL PROTECTED] wrote:
> I would like to reduce the ADC sample rate from the default 62.5 MS/s. I
> have found the set_adc_clk_div in the usrp0_rx class. Is this still
> usable. I tried to use it in the follow:
No. That was only implemented in the Re
I would like to reduce the ADC sample rate from the default 62.5 MS/s. I
have found the set_adc_clk_div in the usrp0_rx class. Is this still
usable. I tried to use it in the follow:
u = usrp.source_c()
u.set_adc_clk_div(6)
and I get errors?
I did 'from gnuradio import usrp0' and still get th
No I have not yet made that change. I have been trying to figure out how
to use it. I don't understand the brief description
/*!
* \brief Enable/disable automatic DC offset removal control loop in FPGA
*
* \param bits which control loops to enable
* \param mask which \p bits to p
At 07:58 PM 11/10/2005 -0800, you wrote:
On Thu, Nov 10, 2005 at 06:23:57PM -0500, cswiger wrote:
>
> But when I try to use it in my script I get a flatline:
>
> self.dut_out = usrp.source_c(0, decim, 4, gru.hexint(0xf0f2f1f0),
The FPGA contains only 2 instance of the DDC, not 4, hence y
On Thu, Nov 10, 2005 at 05:18:26PM -0700, Robitaille, Michael wrote:
> Thanks Eric, I got my direct interface to the USRP working and the
> usrp_oscope.py and ursp_fft.py examples work. I am very glad that the
> software defaults to a Basix Rx DB configuration when it finds no DB.
>
> One item th
> "Daniel" == Daniel O'Connor <[EMAIL PROTECTED]> writes:
Daniel> On Fri, 11 Nov 2005 11:40, David R. Palchak wrote:
>> Am I right in assuming that a modified FPGA design needs to be
>> compiled using the Quartus II toolchain? I ask because as near as I
>> can tell, the only f
