At 07:58 PM 11/10/2005 -0800, you wrote:
On Thu, Nov 10, 2005 at 06:23:57PM -0500, cswiger wrote:
>
> But when I try to use it in my script I get a flatline:
>
> self.dut_out = usrp.source_c(0, decim, 4, gru.hexint(0xf0f2f1f0),
The FPGA contains only 2 instance of the DDC, not 4, hence your problem...
OK - I just remembered that while waking up. Actually it is better to use
two receive channels and switch the ports with the mux - they don't
have to run concurrently. It just saves from having to move test jig
cables around. Changing mux shouldn't change ddc phase.
Tks
--Chuck
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