as MMIO are specifically non-memory mappings that need to be present during
> OS use of RT services. It’s probably a good idea to avoid using MMIO
> regions for all I/O used by Boot Services.
>
>
>
Agree. Will post a patch to fix it.
> A
>
>
>
>
>
> *From:* Tuan
Only need to include Network.dsc.inc to have all network
drivers/components be built. Otherwise, there were missing definition
that prevent them from be built for RiscVVirt platform.
Signed-off-by: Tuan Phan
---
v2:
- Rebase
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 15 +--
1 file
Hi Sami,
Not sure if you can merge this series or let me know who can do it.
Thanks,
From: Sami Mujawar
Date: Thursday, October 5, 2023 at 4:12 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: ardb+tianoc...@kernel.org , ray...@intel.com
, huangm...@linux.alibaba.com ,
suni...@ventanamicro.com
Hi Sunil/ Andrei,
Any comments on this series?
Regards,
On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io wrote:
>
>
> On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <
> andrei.warken...@intel.com> wrote:
>
>> Do you mind sharing a GH branch wit
On Tue, Feb 27, 2024 at 8:42 PM Sunil V L wrote:
> Hi Tuan,
>
> On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote:
> > Hi Sunil/ Andrei,
> > Any comments on this series?
> >
> Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart
&
On Wed, Feb 7, 2024 at 10:15 AM Laszlo Ersek wrote:
> On 2/7/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be
> > supported when Svpbmt extension available.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > .../Library
This series adds support for RISC-V Svpbmt extension.
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will
be mapped to IO and NC mode defined in PBMT field.
v3:
- Addressed Laszlo's comments.
v2:
- Generated patch for each package.
Tuan Phan (3):
MdePkg.dec: RISC-V: Define ove
Define the BIT 2 as the override bit for Svpbmt extension. This will
be used by RISC-V MMU library to support EFI_MEMORY_UC and
EFI_MEMORY_WC.
Cc: Liming Gao
Cc: Michael D Kinney
Cc: Zhiguang Liu
Reviewed-by: Laszlo Ersek
Signed-off-by: Tuan Phan
---
MdePkg/MdePkg.dec | 2 ++
1 file changed
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101 +++---
.../BaseRiscVMmuLib
Disable Svpbmt extension as QEMU not enables it in default config.
Cc: Andrei Warkentin
Cc: Ard Biesheuvel
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Sunil V L
Reviewed-by: Laszlo Ersek
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
1 file changed, 1 insertion(+), 1
Thanks for the detailed review. Please see my comments below.
On Fri, Mar 1, 2024 at 4:14 AM Laszlo Ersek wrote:
> On 3/1/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > supported when Svpbmt extension available.
> >
On Mon, Mar 4, 2024 at 10:01 AM Laszlo Ersek wrote:
> On 3/2/24 00:20, Tuan Phan wrote:
> > Thanks for the detailed review. Please see my comments below.
> >
> > On Fri, Mar 1, 2024 at 4:14 AM Laszlo Ersek > <mailto:ler...@redhat.com>> wrote:
> >
&
mments.
v2:
- Generated patch for each package.
Tuan Phan (4):
MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTN
UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
OvmfPkg/RiscVVirt: Disable Svpbmt extension
MdePkg/
Disable Svpbmt extension as QEMU not enables it in default config.
Cc: Andrei Warkentin
Cc: Ard Biesheuvel
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Sunil V L
Reviewed-by: Laszlo Ersek
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
1 file changed, 1 insertion(+), 1
Define the BIT 2 as the override bit for Svpbmt extension. This will
be used by RISC-V MMU library to support EFI_MEMORY_UC and
EFI_MEMORY_WC.
Cc: Liming Gao
Cc: Michael D Kinney
Cc: Zhiguang Liu
Reviewed-by: Laszlo Ersek
Signed-off-by: Tuan Phan
---
MdePkg/MdePkg.dec | 2 ++
1 file changed
While UINTN defined for RISC-V 64 bits is UINT64, explictly using UINT64
for those variables that clearly are UINT64.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 158 +-
1 file
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 106 ++
.../BaseRiscVMmuLib
Hi Sunil,
On Mon, Mar 18, 2024 at 6:00 AM Sunil V L wrote:
> Hi Tuan,
>
> On Thu, Mar 14, 2024 at 01:19:16PM -0700, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > supported when Svpbmt extension available.
> >
> >
On Tue, Mar 19, 2024 at 9:45 AM Tuan Phan via groups.io wrote:
> Hi Sunil,
>
> On Mon, Mar 18, 2024 at 6:00 AM Sunil V L
> wrote:
>
>> Hi Tuan,
>>
>> On Thu, Mar 14, 2024 at 01:19:16PM -0700, Tuan Phan wrote:
>> > The GCD EFI_MEMORY_UC and EFI_MEMORY_W
StandaloneMmCpu now can supports more platforms like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9
On Fri, Sep 8, 2023 at 12:12 AM Yeo Reum Yun wrote:
> > Signed-off-by: Tuan Phan
> > ---
> > .../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
> > .../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
> > .../StandaloneMmCpu/
StandaloneMmCpu now can supports more platforms like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +--
.../StandaloneMmCpu/StandaloneMmCpu.inf
Update entry point library for Arm to use the new platform independent
StandaloneMmCpu driver.
Signed-off-by: Tuan Phan
---
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
.../Arm/CreateHobList.c | 43 ++-
.../Arm/StandaloneMmCoreEntryPoint.c
This series makes StandaloneMmCpu platform independent so that
other platforms besides ARM/AARCH64 can use it without creating
new driver.
There are two parts in this series:
1. Remove ARM/AARCH64 code from StandaloneMmCpu.
2. Update ARM/AARCH64 entry point library code.
Tuan Phan (2
Hi Sami/Yeo
Do you have any comments on this series?
Regards,
On Thu, Sep 14, 2023 at 4:10 PM Tuan Phan wrote:
> This series makes StandaloneMmCpu platform independent so that
> other platforms besides ARM/AARCH64 can use it without creating
> new driver.
>
> There are two parts
Hi Sami,
Please see my comments below.
On Thu, Sep 28, 2023 at 9:16 AM Sami Mujawar wrote:
> Hi Tuan,
>
> Thank you for this patch.
>
> Please see my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
> On 15/09/2023 12:10 am, Tuan Phan wrote:
>
Sami's comments.
V2:
- Seperated changes between CPU driver and Arm entry point library.
Tuan Phan (2):
StandaloneMmPkg: Make StandaloneMmCpu driver architecture independent
StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
.../Drivers/StandaloneMmCpu/EventHandle.c
StandaloneMmCpu now can supports more architectures like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
Reviewed-by: levi.yun
Reviewed-by: Sami Mujawar
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42
Update entry point library for Arm to use the new architecture independent
StandaloneMmCpu driver.
Signed-off-by: Tuan Phan
Reviewed-by: levi.yun
---
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 +
.../Arm/CreateHobList.c | 43 ++--
.../Arm
Hi Sami,
I just sent the V3 series to address your comments.
Regards,
On Thu, Sep 28, 2023 at 11:16 AM Tuan Phan via groups.io wrote:
> Hi Sami,
> Please see my comments below.
>
> On Thu, Sep 28, 2023 at 9:16 AM Sami Mujawar wrote:
>
>> Hi Tuan,
>>
>> Thank
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATA mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
UefiCpuPkg/Library
If we agree that default should be 10 then i will change it in the next
version.
On Wed, Oct 4, 2023 at 4:36 AM Sunil V L wrote:
> Hi Tuan,
>
> Thanks for the patch!. Adding UefiCpuPkg maintainers.
>
> On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> > Introduce
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
Reviewed-by: Dhaval Sharma
---
Changes:
V2
- Changed default mode to SV57
UefiCpuPkg
https://github.com/pttuan/edk2.git
branch: tphan/riscv_mmu_new_pcd
From: devel@edk2.groups.io on behalf of Andrei Warkentin
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: Kinney, Michael D , Gao, Liming
, Liu, Zhiguang ,
suni...@ventanamicro.com , g
d-off-by: Tuan Phan
---
.../Library/IntrinsicLib/CompilerHelper.c | 41 +++
.../Library/IntrinsicLib/IntrinsicLib.inf | 6 ++-
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 CryptoPkg/Library/IntrinsicLib/CompilerHelper.c
diff --git a/CryptoPkg/Li
https://bugzilla.tianocore.org/show_bug.cgi?id=4103
Signed-off-by: Tuan Phan
Acked-by: Sunil V L
---
V2:
- Add license header.
- Add REF to the bugzilla.
.../Library/IntrinsicLib/CompilerHelper.c | 42 +++
.../Library/IntrinsicLib/IntrinsicLib.inf | 6 ++-
2 files changed, 47 insertions(
On Fri, Dec 16, 2022 at 5:59 PM Pedro Falcato
wrote:
> On Sat, Dec 17, 2022 at 12:06 AM Michael D Kinney <
> michael.d.kin...@intel.com> wrote:
>
>> If that intrinsic is specific to RISCV, then should CompilerHelper.c go
>> into a RiscV64 subdir?
>
>
> Mike and Tuan,
>
> Two comments:
> 1) __ctzd
Tuan,
> -Original Message-
> > From: Tuan Phan
> > Sent: Friday, December 16, 2022 10:48 AM
> > Cc: devel@edk2.groups.io; suni...@ventanamicro.com; Kinney, Michael D <
> michael.d.kin...@intel.com>; Yao, Jiewen
> > ; Wang, Jian J ; Lu,
> Xiaoyu1 ; J
Hi Andrei,
Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu
Will put the link in the cover letter next round.
From: devel@edk2.groups.io on behalf of Andrei Warkentin
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: Kinney, Michael D , Gao
.
>
>
>
> Reviewed-by: Andrei Warkentin
>
>
>
> *From:* devel@edk2.groups.io *On Behalf Of *Tuan
> Phan
> *Sent:* Wednesday, April 19, 2023 5:37 PM
> *To:* devel@edk2.groups.io; Warkentin, Andrei
> *Cc:* Kinney, Michael D ; Gao, Liming <
> gaolim...
On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
> >
> > The flash base address can be added to GCD before this driver run.
> > So only add it if it has not been done.
> >
>
> How do you end up in this si
ion, should the MMU library be in the MdePkg or UefiCpuPkg?
Thanks,
Chao
在 2023/4/15 02:58, Tuan Phan 写道:
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <mailto:tp...@ventanamicro.com>
---
MdePkg/Include/Library/
On Thu, May 25, 2023 at 7:27 AM Ard Biesheuvel wrote:
> On Wed, 24 May 2023 at 20:13, Tuan Phan wrote:
> >
> >
> >
> > On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
> >>
> >> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
> >> >
When the range instruction cache invalidating not supported, the whole
instruction cache should be invalidated instead.
Signed-off-by: Tuan Phan
---
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library
enabled.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp register value
MdePkg/Register: RISC-V: Add satp mode bits shift definition
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
OvmfPkg/VirtNorFlashDxe: Not
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
b/MdePkg
During CpuDxe initialization, MMU will be setup based on the value
get from the PCD satp mode. Default is bare mode.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib
.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index e8fd126cf800..63bc21eb3f60 100644
As MMU will be enabled in CpuDxe, remove the code that set up satp
mode in SEC phase.
Enable SV39 as default mode.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 17 -
2 files changed, 1 insertion(+), 17 deletions
Hi All,Any updates on this patch? Thanks, From: Tuan Phan via groups.ioSent: Monday, March 6, 2023 9:11 AMTo: devel@edk2.groups.ioCc: michael.d.kin...@intel.com; gaolim...@byosoft.com.cn; zhiguang@intel.com; suni...@ventanamicro.com; g...@danielschaefer.me; Tuan PhanSubject: [edk2-devel
accessing them when MMU enabled. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg
When the range instruction cache invalidating not supported, the whole
instruction cache should be invalidated instead.
Signed-off-by: Tuan Phan
---
V2:
- Format with uncrustify.
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion
it’s all one giant line
> of code.
>
>
>
> A
>
>
>
> *From:* Tuan Phan
> *Sent:* Thursday, March 9, 2023 1:20 PM
> *To:* devel@edk2.groups.io
> *Cc:* Kinney, Michael D ; Gao, Liming <
> gaolim...@byosoft.com.cn>; Liu, Zhiguang ;
> suni...@ventanamicr
SATP mode as highest possible that HW supports.
Tuan Phan (6):
MdePkg/BaseLib: RISC-V: Support getting satp register value
MdePkg/Register: RISC-V: Add satp mode bits shift definition
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
b/MdePkg
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf
.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..944b82c84a6e 100644
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe
:
https://github.com/pttuan/edk2.git
Changes in v3:
- Move MMU library to UefiCpuPkg.
- Add Andrei reviewed-by.
Changes in v2:
- Move MMU core to a library.
- Setup SATP mode as highest possible that HW supports.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Include/Library/BaseLib.h b
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64
MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff
.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index
SbiSetTimer expects core tick value.
Signed-off-by: Tuan Phan
---
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions
The timer compare register is 64-bit so simplifying the delay
function.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +--
2 files changed, 28 insertions(+), 35 deletions(-)
diff --git a
On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
> >
> > Normally, DXE driver would add device resource to GCD before start using.
> > But some key resources such as uart, flash base address are being
> accessing
&
On Tue, Jun 6, 2023 at 3:27 AM Sunil V L wrote:
> On Fri, May 26, 2023 at 04:25:18PM -0700, Tuan Phan wrote:
> > The timer compare register is 64-bit so simplifying the delay
> > function.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > MdePkg/Incl
On Tue, Jun 6, 2023 at 10:10 AM Sunil V L wrote:
> On Tue, Jun 06, 2023 at 10:02:08AM -0700, Tuan Phan wrote:
> > On Tue, Jun 6, 2023 at 3:27 AM Sunil V L
> wrote:
> >
> > > On Fri, May 26, 2023 at 04:25:18PM -0700, Tuan Phan wrote:
> > > > The timer co
Only need to include Network.dsc.inc to have all network
drivers/components be built. Otherwise, there were missing definition
that prevent them from be built for RiscVVirt platform.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 15 +--
1 file changed, 1
RiscV uses memory access for IO and MMIO resources, the address limit
is MAX_ADDRESS for both of them.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe
SbiSetTimer expects core tick value.
Cc: Andrei Warkentin
Signed-off-by: Tuan Phan
Reviewed-by: Sunil V L
---
V2: Fixed format issue with uncrustify.
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg
The timer compare register is 64-bit so simplifying the delay
function.
Cc: Andrei Warkentin
Signed-off-by: Tuan Phan
Reviewed-by: Sunil V L
---
V2: Fix format issue with uncrustify.
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 53
On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io wrote:
>
>
> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>
>> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
>> >
>> > Normally, DXE driver would add device resource to GCD before start
&
On Thu, Jun 22, 2023 at 11:41 AM Tuan Phan wrote:
>
>
> On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io ventanamicro@groups.io> wrote:
>
>>
>>
>> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>>
>>> On Sat, 27 May 2023 at 01
.
Changes in v3:
- Move MMU library to UefiCpuPkg.
- Add Andrei reviewed-by.
Changes in v2:
- Move MMU core to a library.
- Setup SATP mode as highest possible that HW supports.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp register value
MdePkg/Register: RISC-V: Add satp
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Reviewed-by: Andrei Warkentin
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
The timer notify function should be called with timer period, not the
value read from timer register.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
b/UefiCpuPkg
Thanks Sunil,
Updated pull request: https://github.com/tianocore/edk2/pull/4585
Please help merge it if no objection.
Thanks,
From: Sunil V L
Date: Wednesday, June 28, 2023 at 7:43 AM
To: Tuan Phan
Cc: devel@edk2.groups.io , andrei.warken...@intel.com
Subject: Re: [PATCH] UefiCpuPkg
On Wed, Jun 28, 2023 at 9:47 AM Sunil V L wrote:
> On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > is the backend flash driver.
> >
> > Signed-off-by: Tuan Phan
> > ---
> &g
As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe so
your suggestion will not work.
On Mon, Jul 3, 2023 at 10:07 PM Sunil V L wrote:
> On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L
> wrote:
> >
On Tue, Jul 4, 2023 at 12:01 AM Sunil V L wrote:
> On Mon, Jul 03, 2023 at 11:45:45PM -0700, Tuan Phan wrote:
> > As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe
> so
> > your suggestion will not work.
> >
> Okay, at least for me, by removi
master.
- Added VirtNorFlashDxe to APRIORI DXE list.
Changes in v3:
- Move MMU library to UefiCpuPkg.
- Add Andrei reviewed-by.
Changes in v2:
- Move MMU core to a library.
- Setup SATP mode as highest possible that HW supports.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
Reviewed-by: Michael D Kinney
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by
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