WorkSpaceAddress and SpareAreaAddress point into MMIO, which isn't
always aligned. Remove the check for block alignment to avoid
false assertions.
Signed-off-by: Sean Rhodes
Change-Id: Ia1c1f44b6a0e7f32cac0d7806e74d729e5d83a6d
---
MdeModulePkg/MdeModulePkg.dec | 2 --
MdeModuleP
v2:
Updated 3/5: "Put SEV logic in separate file" patch.
Added 5/5: "Move the Above1Mb vector allocation to MpInitLibInitialize" patch.
v3:
v2 was sent to wrong mailing list "edk2-de...@lists.01.org".
v3 is created to send to correct mailing list.
All code changes are in https://github.c
global in NASM file is used for symbols that are
referenced in C files.
Remove unneeded global keyword in NASM file.
Signed-off-by: Ray Ni
---
UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm | 8 +---
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 10 ++
2 files changed, 3 insertio
Today's implementation allocates below 1MB memory for the 16bit, 32bit
and 64bit code.
But it's not necessary since now the 32bit and 64bit code run at high
memory no matter in PEI and DXE phase.
The patch simplifies the logic to remove the code that handles the
case when WakeupBufferHigh is 0.
I
The patch does several simplifications:
1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
So the common logic in MpLib.c doesn't need to be aware of
SwitchToRealProc.
As a result, SwitchToRealSize/Offset are removed from
MP_ASSEMBLY_ADDRESS_MAP.
2. Move SwitchToRealProc to Amd
The AP vector consists of 2 parts:
1. the initial 16-bit code that should be under 1MB and page aligned.
2. the 32-bit/64-bit code that can be anywhere in the memory with any
alignment.
The need of part #2 is because the memory under 1MB is temporary
"stolen" for use and will "give" back after
Today's implementation assumes PEI phase runs at 32bit so
the execution-disable feature is not applicable.
It's not always TRUE.
The patch allocates 32bit&64bit code buffer for PEI phase as well.
Signed-off-by: Ray Ni
Cc: Eric Dong
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 2 +-
UefiCpuPkg
Sorry for not being clear on what I mean.
Is it possible to change the platform PCD values and keep these block size
alignment requirements.
Best Regards,
Hao Wu
From: devel@edk2.groups.io On Behalf Of Sean Rhodes
Sent: Monday, May 16, 2022 3:00 PM
To: Wu; Wu, Hao A ; devel@edk2.groups.io
Subje
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A TD
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass
TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will
be introduced in the following commit in this patch-sets ). In that
DXE driver this GUIDed HOB will be parse
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
This is the Cryptographic library instance for SEC. The motivation of
this library is to support SHA384 in SEC phase for Td guest. So only
Hash/CryptSha512.c is included which supports SHA384 and SHA512. Other
cryptographics are added with t
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
This library provides hash service by registered hash handler in Td
guest. Currently only SHA384 is supported. After that the hash value is
extended to Td RTMR registers which is similar to TPM PCRs.
Cc: Jiewen Yao
Cc: Jian J Wang
Cc: Ger
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
TdHobList and Configuration FV are external data provided by Host VMM.
These are not trusted in Td guest. So they should be validated , measured
and extended to Td RTMR registers. In the meantime 2 EFI_CC_EVENT_HOB are
created. These 2 GUIDe
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
SecMeasurementLib is designed to do the measurement in SEC phase. In
current stage there are 2 functions introduced:
- MeasureHobList: Measure the Hoblist passed from the VMM.
- MeasureFvImage: Measure the FV image.
SecMeasurementLibTdx i
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
Add PCDs to records LAML/LASA field in CC EVENTLOG ACPI table.
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Ken Lu
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Reviewed-by: Jiewen Yao
Signed-off-b
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the
event-log information. The event log created by the TD owner contains
the hashes to reconstruct the MRTD and RTMR registers.
Please refer to Sec 4.3.3 in blow link:
https://
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
TdTcg2Dxe mimics the Security/Tcg/Tcg2Dxe. It does below tasks:
- Set up and install CC_EVENTLOG ACPI table
- Parse the GUIDed HOB (gCcEventEntryHobGuid) and create CC event log
- Measure handoff tables, Boot# variables etc
- Measure
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
Enable RTMR based measurement and measure boot for Td guest.
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Ken Lu
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Reviewed-by: Jiewen Yao
Signed-off-by:
The bug discovered was with coreboot, and the PCD values are derived from
the block size of its SMMStore (NvStorage) region. The discussion on the
patch can be found here: https://review.coreboot.org/c/coreboot/+/62990
Hacking the PCDs could work,, but why would we want to keep an incorrect
check?
Sorry Star and Liming,
For the below patch (removing the alignment check for WorkSpace & SpareArea):
https://edk2.groups.io/g/devel/message/89742
Do you think it will impact the FTW service on flash device? Thanks in advance.
Best Regards,
Hao Wu
From: devel@edk2.groups.io On Behalf Of Sean Rh
Reviewed-by: Bob Feng
-Original Message-
From: devel@edk2.groups.io On Behalf Of Jake Garver via
groups.io
Sent: Friday, April 8, 2022 12:59 AM
To: devel@edk2.groups.io; jbra...@nvidia.com; ashishsin...@nvidia.com
Cc: Jake Garver
Subject: [edk2-devel] [PATCH] BaseTools: Fix dependency
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: cbduggap
---
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 +
Hi Ard, Leif,
On Tue, 10 May 2022 at 17:25, Masahisa Kojima via groups.io
wrote:
>
> From: Kazuhiko Sakamoto
>
> Support 4-bytes address for erase and write, so that we can
> access whole region of SPI-NOR Flash(64MiB) implemented on the
> Developerbox.
>
> This commit also fixes the wrong macro
Thanks for correcting format and updating patch per feedbacks!
Just one more comment below inline and please also help to include patch of
IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm
for passing API parameter by RCX.
You might want to create a patch series:
A full-featured SEV-SNP guest will not rely on the AP jump table, and
will instead use the AP Creation interface defined by the GHCB. However,
a guest is still allowed to use the AP jump table if desired.
However, unlike with SEV-ES guests, SEV-SNP guests should not
store/retrieve the jump table a
The Confidential Computing blob defined here is intended to match the
definition defined by linux guest kernel. Previously, both definitions
relied on natural alignment, but that relies on both OVMF and kernel
being compiled as 64-bit. While there aren't currently any plans to
enable SNP support fo
Hi all,
I have. similar symptom in a completely different environment:
- Arch Linux Host
- Arch Linux Guest
- Guest with systems-boot and efi-stub
- Guest with auto-detected efi partition
Symptom is, that after downgrading and re-upgrading the kernel, the reboot will
hang, similar to what Daniel
On 5/16/22 02:14, Ray Ni wrote:
The patch does several simplifications:
1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
So the common logic in MpLib.c doesn't need to be aware of
SwitchToRealProc.
As a result, SwitchToRealSize/Offset are removed from
MP_ASSEMBLY_ADDRESS
On Tue, 10 May 2022 at 10:25, Masahisa Kojima
wrote:
>
> From: Kazuhiko Sakamoto
>
> Support 4-bytes address for erase and write, so that we can
> access whole region of SPI-NOR Flash(64MiB) implemented on the
> Developerbox.
>
> This commit also fixes the wrong macro name. SPINOR_OP_SE and
> SPI
Yes, it has been reviewed by all maintainers. An announcement of the
change was sent to edk2 on April 29th:
https://edk2.groups.io/g/announce/message/291
The series for edk2-platforms has also been out since April 25th:
https://edk2.groups.io/g/devel/message/89308
Thanks,
Michael
On 5/13/2022
I added some contacts that might know more about what ECC requires in
this case. I didn't see any obvious issues in a few of the snippets
reported.
Regards,
Michael
On 5/16/2022 1:15 AM, Chao Li wrote:
Hi All,
There have one last error about EFI coding style error when buiding the
package f
Could I have some reviews of this v2 patch please?
Thanks.
Rebecca Cran
On 5/3/22 14:07, Rebecca Cran wrote:
The DEBUG output in LcdGraphicsBlt is overly verbose, and makes using
the console difficult, for example when using the UiApp.
Since the extra output should no longer be needed, dele
Hi Rebecca,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#89774): https://edk2.groups.io/g/devel/message/89774
Mute This Topic:
Hi Min,
Thank you for this patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#89775): https://edk2.groups.io/g/devel/message/89775
Mute This Topic: https://groups.io/mt/91135111/2165
Hi Min,
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#89776): https://edk2.groups.io/g/devel/message/89776
Mute This Topic: https://groups.io/mt/91135116/2
HI Chasel,
Yes, we don't need to modify esp for LoadMicrocodeDefault. However, this
function does couple of MSR Accesses in b/w that would lead to modify RCX
anyway.
So, if not RSP, we need to use different register to save RCX and consume in
the whole function.
That's why I have not changed t
On Mon, 16 May 2022 at 17:27, Michael Kubacki
wrote:
>
> Yes, it has been reviewed by all maintainers. An announcement of the
> change was sent to edk2 on April 29th:
> https://edk2.groups.io/g/announce/message/291
>
> The series for edk2-platforms has also been out since April 25th:
> https://edk
Hi everyone
I have a question.
Is there a way to put a system to sleep (S3) via UEFI shell?
Checking the UEFIshell spec, there is the reset command, that can be
triggered with parameter -w, that would cause a warm boot. But I am not
sure if warm boot and a S3 resume are the same.
Any comments?
The BaseMemEncryptSevLib functionality was updated to rely on the use of
the OVMF/SEV workarea to check for SEV guests. However, this area is only
updated when running the X64 OVMF build, not the hybrid Ia32/X64 build.
Base SEV support is allowed under the Ia32/X64 build, but it now fails
to boot a
Hi All,
I'm including EFI drivers for an Intel Network card, but this adds a huge
delay in the system startup when the ports are being initialized (the
server has several slots). The network cards will be used only for PXE boot
during the staging/setup process, so I'm thinking of adding a configur
On Fri, Apr 15, 2022 at 08:07:08AM +0800, Min Xu wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
>
> Bad IO performance in SEC phase is observed after TDX features was
> introduced. (after commit b6b2de884864 - "MdePkg: Support mmio for
> Tdx guest in BaseIoLibIntrinsic").
>
> Th
Add a new PCD to be able to configure whether newly detected boot options
are to be added at the beginning of the current boot options list or at
the end.
Signed-off-by: Ashish Singhal
---
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c| 6 +-
.../Library/UefiBootManagerLib/Uefi
*Tools, CI, Code base construction meeting series*
*When:*
05/16/2022
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://github.com/tianocore/edk2/discussions/2614
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1496535 )
*Description:*
TianoCore community,
Micros
As far as I know, there is no general(safe) way to do S3 in Uefi shell. There
is no AML interpreter driver in UEFI shell to run the platform ASL code.
The warm reset is different from the S3 resume.
Thanks
Steven Shi
From: devel@edk2.groups.io On Behalf Of Rafael Machado
Sent: Tuesday, May
Thanks for clarification!
In this case, please use "mov rsp, rcx" to support 64bit addressing.
Thanks,
Chasel
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Tuesday, May 17, 2022 12:33 AM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Zeng, Star
> ; S,
On May 17, 2022 6:22 AM, dann frazier wrote:
> I ran through our tests on stable-202205-rc1, and I'm finding that all of the
> tests using 2M FD_SIZE & SMM_REQUIRE=TRUE are failing with QEMU
> hanging w/o output. Equivalent tests w/ 4M FD_SIZE are working fine. I
> bisected it down to this commit,
*Reminder: TianoCore Bug Triage - APAC / NAMO*
*When:*
05/17/2022
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed77
BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:CANCELLED
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
LAST-MODIFIED:20220317T223602Z
TZURL:http://tzurl.org/zoneinfo-outlook/America/Los_Angel
Add RedfishEventLib to Redfish client package. This library provides
interface for Redfish feature drivers to listen to Redfish event
such as the event before provisioning and the event after
provisioning. Feature driver can perform additional operation before
and after Redfish provisioning.
Signe
Hi Judah,
Do you have reference information for the following?
1. Overall boot time impact for a sample variable store?
- In particular:
- Initial HMAC calculation/verification time.
- Non-volatile write impact time to caluclate new store HMAC value
and update MetaDataHmacVar.
- Variab
From: Ankit Sinha
Adds new PCDs to allow entries in FADT to be customized during platform
integration. Board packages will can update these PCDs during boot.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Ankit Sinha
---
Platform/Intel/MinPlatformPkg/Acpi/Ac
Add RedfishVersionLib to Redfish client package. This library provides
interface for Redfish feature drivers to get Redfish version on BMC.
Signed-off-by: Nickle Wang
Cc: Abner Chang
---
.../Include/Library/RedfishVersionLib.h | 30 +++
RedfishClientPkg/Include/RedfishBase.h| 16
Liming, will you push both?
I put a rebased edk2-platforms with all the review tags for that series
here:
https://github.com/makubacki/edk2-platforms/commits/add_variableflashinfolib_to_platforms
Thanks,
Michael
On 5/16/2022 1:36 PM, Ard Biesheuvel wrote:
On Mon, 16 May 2022 at 17:27, Micha
Can someone seriously respond?
This was approved over 3 weeks ago and sent 5 weeks ago. I know Ankit
now has a similar change out but I'd like to see if this can get in and
that be rebased on it since this has been out for so long and has the
primary change needed for our integration.
Thanks
*** BLURB HERE ***
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
FSP_TEMP_RAM_INIT consume input parameter using RCX.
cbduggap (2):
IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention
IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Conv
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: cbduggap
---
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 +
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: cbduggap
---
.../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm | 4 +++-
1 file changed, 3 insertions(+), 1 del
Michael:
Yes. I can. Where is the change for Edk2?
Thanks
Liming
> -邮件原件-
> 发件人: Michael Kubacki
> 发送时间: 2022年5月17日 12:14
> 收件人: devel@edk2.groups.io; a...@kernel.org
> 抄送: gaoliming ; Abner Chang
> ; Andrew Fish ; Anthony Perard
> ; Ard Biesheuvel ;
> Benjamin You ; Brijesh Singh
> ; E
Thanks Chinni!
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Tuesday, May 17, 2022 1:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali
> Subject: [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INI
Thanks Chinni!
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Tuesday, May 17, 2022 1:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali
> Subject: [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_
60 matches
Mail list logo
