On 07/10/2021 16:06, Leif Lindholm wrote:
On Wed, Oct 06, 2021 at 19:55:53 +0700, Nhi Pham wrote:
Would it be possible for PHYLib to link in ArmArchTimerLib directly
and wrap this there instead? Something about this integration just
feels kind of backwards to me.
Thanks Leif. That's great idea.
On Wed, Oct 06, 2021 at 19:55:53 +0700, Nhi Pham wrote:
> > Would it be possible for PHYLib to link in ArmArchTimerLib directly
> > and wrap this there instead? Something about this integration just
> > feels kind of backwards to me.
>
> Thanks Leif. That's great idea.
>
> I will wrap it and re-s
Hi Leif,
On 06/10/2021 02:59, Leif Lindholm via groups.io wrote:
On Mon, Oct 04, 2021 at 19:03:40 +0700, Nhi Pham wrote:
Hi Leif,
There are two comments that I would like to clarify with you.
On 23/09/2021 20:49, Leif Lindholm wrote:
+VOID
+Ac01PcieMmioWr (
+ UINT64 Addr,
+ UINT32 Val
+ )
On Mon, Oct 04, 2021 at 19:03:40 +0700, Nhi Pham wrote:
> Hi Leif,
>
> There are two comments that I would like to clarify with you.
>
> On 23/09/2021 20:49, Leif Lindholm wrote:
> > > +VOID
> > > +Ac01PcieMmioWr (
> > > + UINT64 Addr,
> > > + UINT32 Val
> > > + )
> > > +{
> > > + Ac01PcieCsr
Hi Leif,
There are two comments that I would like to clarify with you.
On 23/09/2021 20:49, Leif Lindholm wrote:
+VOID
+Ac01PcieMmioWr (
+ UINT64 Addr,
+ UINT32 Val
+ )
+{
+ Ac01PcieCsrOut32Serdes ((VOID *)Addr, (UINT32)Val);
+}
+
+VOID
+Ac01PciePuts (
Wait, what. We have *two* sets of out
Hi Leif,
Thanks a lot for your review. We are heading to improve the Ac01PcieLib
and addressing your comments in the PciSegmentLib, by decoupling the
Ac01PcieLib into hierarchical modules. Hoping it will look better to you.
Best regards,
Nhi
On 28/09/2021 17:34, Leif Lindholm wrote:
Apart
Apart from the request to break out Ac01PcieConfigRW and
Ac01PcieCfgIn/Out# I noticed a further thing.
On Wed, Sep 15, 2021 at 22:55:11 +0700, Nhi Pham wrote:
> +/**
> + Get RootBridge disable status.
> +
> + @param[in] HBIndex Index to identify of PCIE Host bridge.
> + @param[in
Hi Nhi,
I think all of my comments up to here have been reasonably simple.
This patch I have not reviewed before, so they could be more detailed.
If you'd like to submit a v4 of 1-11, we could possibly merge those
and reduce the churn a bit.
Anyway, review following:
On Wed, Sep 15, 2021 at 22:
From: Vu Nguyen
Provides essential functions to initialize the PCIe Root Complex of
Ampere Altra processor.
Cc: Thang Nguyen
Cc: Chuong Tran
Cc: Phong Vo
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Ard Biesheuvel
Cc: Nate DeSimone
Signed-off-by: Vu Nguyen
---
Silicon/Ampere/AmpereAltraP
