Reviewed-by: Yuwei Chen
> -Original Message-
> From: Kuo, Ted
> Sent: Friday, July 5, 2024 5:32 PM
> To: devel@edk2.groups.io
> Cc: Liming Gao ; Feng, Bob C
> ; Chen, Christine
> Subject: [edk2-devel][PATCH][edk2-staging] BaseTools: Fix BaseTools
> compilation issues
>
> https://bugzil
On Wed, Jul 10, 2024 at 04:56 PM, Gerd Hoffmann wrote:
>
> Has been reported recently on qemu-devel, so it could very well be you
> are hitting a regression on the qemu side.
Hi Gerd,
Thanks for your answer but I'm not using QEMU. The platform I am working on is
CFL.
take care,
Hamit Can
-=
Hello,
We are pleased to announce the launch of a project by 3mdeb aimed at integrating
UEFI Capsule Update for coreboot with EDK II as a payload. This initiative aims
to bring the capsule-based update method, providing an alternative to the
traditional flashrom-based method, which becomes more an
From: Xiong Yining
To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.
We can get the CPU topology information via SMC.
Signed-off
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Based on Ampere platform core. Added support for cpus with FEAT_CCIDX
(Neoverse-V1 and above).
Reported-by: Jonathan Cameron
Signed-off-by: Marc
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 243 +++
During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.
So topology moves from:
Socket -> Clusters -> Cores + Caches -> Threads (if exist)
to:
Socket -> Clusters -> Cores -> Caches + Threads (if e
ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard/SbsaQemuAcpi
We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.
The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmw
Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one core.
As SMC calls can return up to 4 return values, the number of sockets,
cluste
On 10.07.2024 19:52, Marcin Juszkiewicz via groups.io wrote:
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Code taken from Ampere platform core.
Reported-by: Jonathan Cameron
Signed-off-by:
We read CPU topology from TF-A so there is no need to keep fake values
anymore.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 3 ---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4
Silicon/Qemu/SbsaQemu/Drive
EDK2 takes information from TF-A. How it got that info does not interest
us.
Signed-off-by: Marcin Juszkiewicz
---
.../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemu
: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240711-b4-cleanups-9f28a3e38597
Best regards,
--
Marcin Juszkiewicz
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