> The name of EDKII_MEMORY_ACCEPT_PROTOCOL indicates it is only used in edk2.
Ah, yes I was basing my changes off probably a very old version of
TDVF's patches that used the EFI_ naming convention, so folks looking
at my branch might have been expecting that it'd be standardized.
Cool. Just the on
Reviewed-by: Ray Ni
> -Original Message-
> From: Liu, Zhiguang
> Sent: Wednesday, October 12, 2022 3:28 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Dong, Eric
> ; Ni, Ray ; Kumar, Rahul R
>
> Subject: [PATCH V2] UefiCpuPkg:Add RegisterExceptionHandler in
> PeiCpuExceptionHandler
Liming,
Thank you. If EDK2 have merged new commit, I will rebase the PR in a few days.
Please let me know if you have any questions.
Thanks,
Chao
On 10月 12 2022, at 8:20 早上, "gaoliming" wrote:
> Chao:
>
> I will check this PR, and merge it this week if no other comment.
>
> Thanks
> Li
Below code will calculate the reserved bus number for the each PF.
Based on the VF routing ID algorithm, PFRid and LastVF in below code
already sure that "All VFs and PFs must have distinct Routing IDs".
PF will be assigned Routing ID based on secBusNumber, ReservedBusNum
will add into SubBusNumbe
If a device which support both features SR-IOV/ARI has multi
functions, which maybe support 8-255. After enable ARI forwarding in
the root port and ARI Capable Hierarchy in the SR-IOV PF0.
The device will support and expose multi functions(0-255) with ARI ID routing.
In next device loop in below f
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095
Updates several debug macros in TigerlakeSiliconPkg to correctly
match print specifiers to actual arguments.
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Heng Luo
Signed-off-by: Michael Kubacki
---
Silicon/Intel/Tiger
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095
Updates several debug macros in KabylakeSiliconPkg to correctly
match print specifiers to actual arguments.
Cc: Chasel Chiu
Cc: Sai Chaganty
Signed-off-by: Michael Kubacki
Reviewed-by: Nate DeSimone
---
Silicon/I
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095
Updates several debug macros in CoffeelakeSiliconPkg to correctly
match print specifiers to actual arguments.
Cc: Chasel Chiu
Cc: Sai Chaganty
Signed-off-by: Michael Kubacki
---
Silicon/Intel/CoffeelakeSiliconPkg
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095
Fixes several debug macros in Silicon/Intel that have a mismatched
number of print specifiers to arguments.
The original author's intention is not always 100% obvious. Though,
this series is relatively straightforward
Thanks, I took the approach that no one seemed to miss bad/missing
information. I'll send a v2 with these suggestions.
On 10/11/2022 8:37 PM, Nate DeSimone wrote:
Hi Michael,
Please see feedback inline.
Thanks,
Nate
-Original Message-
From: devel@edk2.groups.io On Behalf Of Michael
Hi,
> I think we could do the following in ArmVirtPkg:
>
> --- a/ArmVirtPkg/ArmVirt.dsc.inc
> +++ b/ArmVirtPkg/ArmVirt.dsc.inc
> [PcdsFixedAtBuild.common]
> +!ifdef $(FIRMWARE_VER)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
> +!endif
Yes, that idea looks g
Hi Gerd,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 12/10/2022 11:39 am, Gerd Hoffmann wrote:
On Wed, Oct 12, 2022 at 07:35:23AM +, Oliver Steffen wrote:
Initialize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FI
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)
diff
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RiscVVirt is created to support EDK2 for RISC-V qemu
virt machine platform. Add maintainer entries.
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Signed-off-by: Sunil V L
---
Maintainers.txt | 4
1 file changed, 4 inserti
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add infrastructure files to build edk2 for RISC-V qemu virt machine.
- EDK2 will boot as S-mode payload of opensbi.
- It supports building
either code and variables in unified flash or in two separate drives
via build time option UNIFIE
Currently, when dealing with small updates that can be written out
directly (i.e., if they only involve clearing bits and not setting bits,
as the latter requires a block level erase), we iterate over the data
one word at a time, read the old value, compare it, write the new value,
and repeat, unle
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V needs NorFlashDxe driver for qemu virt machine. The
ArmPlatformPkg has this driver but migrating it to generic
package like MdeModulePkg introduces circular dependencies.
So, add NorFlashDxe driver in OvmfPkg which is mostly the
copy
Switching to array mode (i.e., ROM memory mode rather than NOR flash
programming mode) is rather costly when running under KVM emulation, as it
involves setting up the read-only memslot in the hypervisor's stage 2
page tables. So let's avoid jumping between modes unnecessarily, and
only switch back
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformBootManagerLib has been moved to OvmfPkg so that other
CPU architectures can reuse. So, update existing paths with the
new location.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-off-by: Sunil V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from ArmVirtPkg since it is required for
other architectures also. It uses OVMF specific PCD variables.
Also add the instance for single flash drive which has
both code and variables. This is copied from SbsaQemu.
Cc:
This library is required by NorFlashDxe. Since it will be used by
both virtual and real platforms, migrate this library to
MdeModulePkg.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Abner Chang
Cc: Daniel Schaefer
Cc: Jian J Wang
Cc: Liming Gao
Cc: Andrew Fish
Cc: Michael D Kinney
Signed-off-b
Migrate NorFlashPlatformLib.h to MdePkg and add a Null
instance of the NorFlashPlatformLib library in MdePkg.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Andrew Fish
Signed-off-by: Sunil V L
---
ArmPlatformPkg/ArmPlatformPkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This module is required by other architectures like RISC-V.
Hence, move this to OvmfPkg.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
ArmVirtPkg/ArmVirtPkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformBootManagerLib in ArmVirtPkg is required for RISC-V
also. So, move it to OvmfPkg.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Jordan Justen
Signed-off-by: Sunil V L
---
OvmfPkg/
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformHasAcpiDtDxe is required by other architectures also.
Hence, it is moved to OvmfPkg. So, update the consumers of this
module with the new location.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-o
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/UefiCpuPkg.dsc| 3 +
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add the support for this protocol which is defined in the spec:
https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf
Cc: Eric Dong
C
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is migrated from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 11 ++
UefiCpuPkg/CpuDxe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, CpuDxe supports only X86 architecture. To add
support for other architectures like RISC-V, this need to
be refactored.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/CpuDxe/CpuDxe.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
.../DxeCpuExceptionHandlerLib.inf | 7 +-
.../SecPeiCpuExceptionHandlerLib.inf | 7 +-
.../RiscV64/CpuExceptionHandlerLi
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the CpuExceptionHandlerLib library supports only X86.
Refactor the library to allow adding other CPU architectures.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
.../DxeCpuExceptionHandlerLib.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
.../Library/CpuTimerLib/BaseCpuTimerLib.inf | 3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, CpuTimerLib library supports only X86 architecture.
Refactor to allow other CPU architectures.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
OvmfPkg/PlatformPe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, PlatformPei supports only X86 architecture. So,
refactor it to allow other CPU architectures.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
OvmfPkg/PlatformPei/PlatformPe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add the SEC module for RISC-V. EDK2 is launched as the payload
for machine mode firmware in RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Min X
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the Sec module supports only X86 architecture.
Refactor the module to allow other CPU architectures.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomle
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Rebecca Cran
Cc: Peter Grehan
Cc: Daniel Schaefer
Signed-off-by: S
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the ResetSystemLib library supports only X86 architecture.
Refactor it to allow adding other CPU architectures like RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Rebecca Cran
Cc: Peter Gre
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim
but added as part of library instead of a separate module.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Daniel Schaefer
Signe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, PlatformInitLib supports only X86 architecture. So,
refactor to allow adding other architectures like RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
.../PlatformIn
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This library is required to make SBI ecalls from the S-mode EDK2.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
---
MdePkg/MdePkg.dec | 4 +
MdePkg/MdePkg.dsc
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Daniel Schaefer
Signed-off-by:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition and the header file required.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
---
MdePkg/MdePkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.
Cc: Daniel Schaefer
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
---
.../Include/Register/RiscV64
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add support for RISC-V qemu virt machine. Most of the changes are migrated from
edk2-platforms repo and followed the latest guidelines for EDK2 code
structuring.
The changes at a high level are,
1) MdePkg:
- Add RISC-V register de
On Wed, Oct 12, 2022 at 07:35:23AM +, Oliver Steffen wrote:
> Initialize
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> with with the value of the variable "FIRMWARE_VER"
> in all flavors of ArmVirtPkg.
>
> This behavior is already implemented in ArmVirtXen.dsc.
> It allows specif
Hi Oliver,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 12/10/2022 08:35 am, Oliver Steffen wrote:
Initialize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER"
in all fla
Hi, Mike
Thank you for your reply. We add a PCD because we want to dynamic disable the
terminal through setupbrowser.
But as you said, the standard way is using console variables to manage it. We
did not think about it before, we will have a try.
Thanks
Wenyi
On 2022/10/11 21:58, Kinney, Mich
On Tue, Oct 11, 2022 at 09:34:17AM -0600, Rebecca Cran wrote:
> On 10/11/22 01:59, Gerd Hoffmann wrote:
> >
> > Next question is how to set them. I think it makes sense to have some
> > sensible defaults, but still allow to override them. MdeModulePkg
> > defines them to empty strings (except ve
Thanks Mike. Agree with you.
For the series, Acked-by: Jiewen Yao
Just FYI: I have merged rest pending CryptoPkg patches.
Please rebase when you submit next version.
Thank you
Yao Jiewen
> -Original Message-
> From: Kinney, Michael D
> Sent: Wednesday, October 12, 2022 10:23 AM
> To:
Reviewed-by: James Lu
Thanks,
James
-Original Message-
From: devel@edk2.groups.io On Behalf Of Sean Rhodes
Sent: Friday, October 7, 2022 4:22 AM
To: devel@edk2.groups.io
Cc: Rhodes, Sean ; Dong, Guo ; Ni,
Ray ; Lu, James ; Guo, Gua
Subject: [edk2-devel] [PATCH] UefiPayloadPkg: Make
ArmVirtXen.dsc allows setting the firmware version
string in gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
via FIRMWARE_VER variable conveniently on the build command line.
These two patches add this behavior to all .dsc files in ArmVirtPkg
and OvmfPkg.
Signed-off-by: Oliver Steffen
O
Initialize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER"
in all flavors of OvmfPkg.
This behavior is already implemented in ArmVirtXen.dsc.
It allows specifying the firmware version string on the
build command line with -D FIRMARE_VER=..
Initialize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER"
in all flavors of ArmVirtPkg.
This behavior is already implemented in ArmVirtXen.dsc.
It allows specifying the firmware version string on the
build command line with -D FIRMARE_VER
The PEI instance of the CpuExceptionHandlerLib didn't implement the
RegisterCpuInterruptHandler() API. This patch adds the missing API.
Signed-off-by: Zhiguang Liu
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
---
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c | 38
++
Hi Gaoliming,
Kindly let us know the review status of this issue.
Thanks,
Prakash K
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