From: Jason1 Lin
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3928
Windows-based system using signtool.exe to sign the capsule.
Add the support to using "--subject-name" argument to assign the
subject name used to sign the capsule file.
This argument would pass to signtool.exe as a part o
*Reminder: TianoCore Bug Triage - APAC / NAMO*
*When:*
05/31/2022
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed77
pushed as 71dab4b0eaa4214586b9e03c1c42c7562095353c
Mike
> -Original Message-
> From: Kinney, Michael D
> Sent: Tuesday, May 31, 2022 4:45 PM
> To: devel@edk2.groups.io; Jayaprakash, N ; Kinney,
> Michael D
> Subject: RE: [edk2-devel] [edk2-libc Patch 1/1]
> AppPkg\Applications\Python\
Reviewed-by: Michael D Kinney
I do see that there are 3 documentation files in Python-3.6.8.
One is from the Python project. The other 2 look like they both
contain EDK II build instructions. Perhaps these should be combined into
a single file for EDK II builds for all supported tool chains an
Hi all,
Following https://edk2.groups.io/g/devel/message/89684, I want to add
sanitizer support to upstream EDK2. Doing this in a non-intrusive way would
mean that I need to force all modules to depend on the UBSAN/ASAN
implementation lib and force them to use a specific compile flag. Is there
a w
Ping. Please review it now that the freeze is over.
Thanks,
Pedro
On Wed, May 11, 2022 at 6:44 PM Pedro Falcato via groups.io wrote:
> Ping. Could someone review it?
>
> On Mon, Apr 25, 2022 at 6:13 PM Pedro Falcato via groups.io
> wrote:
>
>> Ping. If someone could take a look, it would be mu
Ping. Please review now that the stable freeze is over.
On Wed, May 11, 2022 at 6:42 PM Pedro Falcato via groups.io wrote:
> Ping. Could someone review these patches?
>
> On Mon, Apr 25, 2022 at 6:14 PM Pedro Falcato via groups.io
> wrote:
>
>> Ping. If someone could take a look, it would be mu
[AMD Official Use Only - General]
Hello Nikunj,
But, yes this needs to be fixed.
Thanks,
Ashish
-Original Message-
From: Kalra, Ashish
Sent: Tuesday, May 31, 2022 12:51 PM
To: Dadhania, Nikunj ; devel@edk2.groups.io
Cc: dovmu...@linux.vnet.ibm.com; brijesh.si...@amd.com; to...@ibm.com;
[AMD Official Use Only - General]
Hello Nikunj,
That is true, but there is no SEV live migration happening before GHCB pages
are re-setup and the hypercalls are invoked again for GHCB pages from
the guest kernel after it checks the live migration runtime environment flag
setup by OVMF.
Thanks,
Hi Ashish,
I missed the v8 and replied on v7.
On 4/5/2022 11:02 PM, Ashish Kalra via groups.io wrote:
> From: Ashish Kalra
>
> Mark the SEC GHCB page (that is mapped as unencrypted in
> ResetVector code) in the hypervisor's guest page encryption
> state tracking.
>
> Cc: Jordan Justen
> Cc: A
Hello,
We would like to confirm whether any Coverity tests are performed for EDK2
CryptoPkg?
If no, please confirm if we can contribute the Coverity fix to edk2.
Thanks
Prarthana
-The information contained in this message may be confidential and proprietary
to American Megatrends (AMI). This co
Hi Ashish,
On 8/19/2021 7:36 PM, Ashish Kalra via groups.io wrote:
> From: Ashish Kalra
>
> Mark the SEC GHCB page (that is mapped as unencrypted in
> ResetVector code) in the hypervisor's guest page encryption
> state tracking.
>
> Cc: Jordan Justen
> Cc: Ard Biesheuvel
> Signed-off-by: Ashi
From: Zhihao Li
REF： https://bugzilla.tianocore.org/show_bug.cgi?id=3854
In UefiCpuPkg, there are a new Protocol with the new service
SmmWaitForAllProcessor(), which can be used by SMI handler
to optionally wait for other APs to complete SMM rendezvous in
relaxed AP mode.
This patch use the new
Hi,
> To make things worse I see that if we return success there EDK2 will
> actually go ahead and start assigning trash addresses to the device
> and enable IO space decoding in case of the PCI root port which means
> that device will try to decode invalid IO ranges.
> Logs:
> PciBus: Resourc
Hi,
> yes:) Actually there is no split at all. The 4K page table is created in the
> very beginning(before setting to cr3).
> So, no TLB cache issue at all.
> > I think doing a linux-style page split will be the more robust solution.
>
> Thanks for explaining the linux behavior.
>
> Intel's
According to GHCI Spec Table 2-1, in TDVMCALL R10 should be cleared
to 0 in input operands, and be checked for the return result.
https://cdrdv2.intel.com/v1/dl/getContent/726790
Cc: Erdem Aktas
Cc: Gerd Hoffmann
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Signed-off-by: Min Xu
---
During the integration test with TDX upstreaming KVM/QEMU there are 2
issues are found. This patch-set are to fix these 2 issue.
- Fix TDVMCALL error in ApRunLoop.nasm
- Search EFI_RESOURCE_MEMORY_UNACCEPTED for Fw hoblist
Cc: Erdem Aktas
Cc: Gerd Hoffmann
Cc: James Bottomley
Cc: Jiewen Yao
In current TDVF implementation all unaccepted memory passed in Hoblist
are tagged as EFI_RESOURCE_MEMORY_UNACCEPTED. They're all accepted before
they can be accessed. After accepting memory region, the Hob ResourceType
is unchanged (still be EFI_RESOURCE_MEMORY_UNACCEPTED).
TDVF Config-B skip PEI
> > I am not quite sure how Linux handles such case?
>
> Oh, lovely. CPU bugs lurking indeed. linux has this longish comment
> (see mm/huge_memory.c, in the middle of the __split_huge_pmd_locked()
> function):
>
> /*
> * Up to this point the pmd is present and huge and userland
Hi,
> I am not quite sure how Linux handles such case?
Oh, lovely. CPU bugs lurking indeed. linux has this longish comment
(see mm/huge_memory.c, in the middle of the __split_huge_pmd_locked()
function):
/*
* Up to this point the pmd is present and huge and userland has the
Gerd,
We saw page fault in the following situation:
* a 2M page entry (with present bit set) points to some memory [p, p+2M)
* Firmware code wants to mark [p, p+4k) as read-only
* Firstly [p, p+2M) is split to 512 page-entries with each pointing to 4K
memory (with present bit set still)
* Secondly
On Tue, May 31, 2022 at 01:39:37PM +0800, Zhiguang Liu wrote:
> There is a concern case that stack and a proteced DXE memory range is in
> the same 2M Page Table entry, and somehow CPU doesn't flash the page
> table entry cache for stack, and causes Page fault when using stack.
Can you clarify the
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