On Tue, May 31, 2022 at 01:39:37PM +0800, Zhiguang Liu wrote: > There is a concern case that stack and a proteced DXE memory range is in > the same 2M Page Table entry, and somehow CPU doesn't flash the page > table entry cache for stack, and causes Page fault when using stack.
Can you clarify the "somehow" please? Are we discussing a workaround for a cpu bug here? If not this sounds like a tlbflush instruction is missing somewhere ... take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90100): https://edk2.groups.io/g/devel/message/90100 Mute This Topic: https://groups.io/mt/91446026/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
