https://bugzilla.tianocore.org/show_bug.cgi?id=3860
Signed-off-by: Abner Chang
Co-authored-by: Daniel Schaefer
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Sunil V L
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Chao Li
---
UefiCpuPkg/UefiCpuPkg.ci.yaml | 61 +++
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
This is the first step of reworking on UefiCpuPkg in order to
accommodating all processor architectures in UEfiCpuPkg.
Classify UefiCpuPkg modules to IA32 and X64 sections in DSC file.
Move the module to Common section if more than one archs can
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
(This is migrated from edk2-platforms:Silicon/RISC-V)
EDK2 RISC-V OpenSBI library which pull in external source files under
UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process.
Signed-off-by: Abner Chang
Co-authored-by: Danie
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
(This is migrated from edk2-platforms:Silicon/RISC-V)
Add RISC-V opensbi as the submoudle under UefiCpuPkg/Library/RISC-V
Signed-off-by: Abner Chang
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Cc: Sunil V L
Cc: Andrew Fish
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
Add BaseUefiCpuLib instance for RISC-V RISCV64 arch.
Signed-off-by: Abner Chang
Co-authored-by: Daniel Schaefer
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Sunil V L
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Chao Li
--
(This is migrated from edk2-platforms:Silicon/RISC-V)
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
RISC-V processor architecture definitions.
Signed-off-by: Abner Chang
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Cc: Sunil V L
Cc: Andrew Fish
Cc: Leif Lindholm
Cc:
https://bugzilla.tianocore.org/show_bug.cgi?id=3860
This is the project having rework on UefiCpuPkg in order to support a variety
of processor architectures. Some modules under UefiCpuPkg are required to be
abstract for the different archs.
The first step is to classify UefiCpuPkg modules to IA32
Reviewed-by: Jiewen Yao
> -Original Message-
> From: Li, Zhihao
> Sent: Friday, March 18, 2022 12:22 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Wang, Jian J ;
> Lu, Xiaoyu1 ; Jiang, Guomin ;
> Fu, Siyuan
> Subject: [PATCH v7 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash25
Main Changes :
1.support decimal type version number when running ecc check.
Wenyi Xie (1):
BaseTools:Support decimal version number in ECC check
BaseTools/Source/Python/Ecc/MetaFileWorkspace/MetaFileParser.py | 18
+++---
1 file changed, 15 insertions(+), 3 deletions(-)
--
2.20
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3872
When doing ecc inf version check, the decimal type version number
like 1.27 is treated as invalid version.
So the code should be updated to support decimal type version number.
Cc: Bob Feng
Cc: Liming Gao
Cc: Yuwei Chen
Signed-off-by: Wen
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.
Passed CI test.
Onprotocol version code passed test.
Cc: Jiewen Ya
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Create PR https://github.com/tianocore/edk2/pull/2647 to merge it.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 gaoliming
> 发送时间: 2022年3月8日 9:42
> 收件人: 'Abdul Lateef Attar' ; devel@edk2.groups.io
> 抄送: 'Michael D Kinney' ; 'Zhiguang Liu'
>
> 主题: [edk2-devel] 回复: [PATCH v3 1/1] M
Sorry. I forgot to update. I have create the PR twice but the open-CI failed.
Can you check? https://github.com/tianocore/edk2/pull/2568
Thanks,
Zhichao
> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef)
> Sent: Thursday, March 17, 2022 3:10 PM
> To: Gao, Zhichao ; devel@edk
OK
> -Original Message-
> From: Yao, Jiewen
> Sent: Friday, March 18, 2022 9:59 AM
> To: Li, Zhihao ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan ;
> Yao, Jiewen
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256Hash
Yes. It seems we missed RsaPssSign and RsaPssVerify in previous patch. Sigh...
Would you please help to add them?
> -Original Message-
> From: Li, Zhihao
> Sent: Friday, March 18, 2022 9:53 AM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ;
Hi,
Something I've just noticed: edk2-libc also ships its own intrinsics (
https://github.com/tianocore/edk2-libc/blob/master/StdLib/LibC/CRT/Gcc.c)
I know edk2-libc is not part of the core edk2 repo but I think we should
keep this in mind when this patch set gets merged.
On Fri, Mar 18, 2022 at
Build CryptoPei and CryptoSmm driver report this error.
INFO - /home/vsts/work/1/s/CryptoPkg/Driver/Crypto.c:4707:3: error:
initialization of 'BOOLEAN (__attribute__((ms_abi)) *)(void *, const UINT8 *,
UINTN, UINT16, UINT16, UINT8 *, UINTN *)' from incompatible pointer type
'BOOLEAN (__attri
Gerd:
I suggest to submit the different BZs for those tasks. This patch set is
the first stage. Future enhancement can be added later.
If no more comment for the first stage, this patch set can be merged
first.
Thanks
Liming
> -邮件原件-
> 发件人: Gerd Hoffmann
> 发送时间: 2022年3月16日 17:46
> 收件
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Kun Qin
> 发送时间: 2022年3月16日 12:00
> 收件人: devel@edk2.groups.io
> 抄送: Jiewen Yao ; Eric Dong ;
> Ray Ni ; Jian J Wang ; Liming Gao
>
> 主题: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: PiSmmCore: Inspect
> memory guarded with pool
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: Wu, Hao A
> 发送时间: 2022年3月15日 14:08
> 收件人: devel@edk2.groups.io; Kinney, Michael D
> ; Gao, Liming ;
> Liu, Zhiguang ; Ni, Ray
> 主题: RE: [PATCH v2] MdePkg/AcpiXX.h: Update Error Severity type for
> Generic Error Status Block
>
> Hello,
>
> Any fe
Min:
This patch is good. I have no other comments in MdePkg. Reviewed-by:
Liming Gao
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Min Xu
> 发送时间: 2022年3月17日 13:32
> 收件人: devel@edk2.groups.io; Xu, Min M
> 抄送: Michael Roth ; Ni, Ray ;
> Kumar, Rahul1 ; Dong, Eric ;
> James Botto
What is root cause of failure?
I don't understand.
> -Original Message-
> From: Li, Zhihao
> Sent: Friday, March 18, 2022 12:27 AM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new ha
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDX the guest firmware is designed to publish a multiprocessor-wakeup
structure to let the guest-bootstrap processor wake up guest-application
processors with a mailbox. The mailbox is memory that the guest firmware
can reserve so each gu
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
OvmfPkg/PlatformPei is updated to support Tdx guest. There are below
major changes.
- Set Tdx related PCDs
- Publish Tdx RamRegions
In this patch there is another new function BuildPlatformInfoHob ().
This function builds EFI_HOB_PLATFORM
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Guest Physical Address (GPA) space in Td guest is divided into private
and shared sub-spaces, determined by the SHARED bit of GPA. This PCD
holds the shared bit mask. Its default value is 0 and it will be set
in PlatformPei driver if it is o
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
There are below changes in PlatformInitLib for Tdx guest:
1. Publish ram regions
In Tdx guest, the system memory is passed in TdHob by host VMM. So
the major task of PlatformTdxPublishRamRegions is to walk thru the
TdHob list and transfer t
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
If IA32_ERER.NXE has already been set, skip setting it again.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Gerd Hoffmann
Acked-by: Gerd Hoffmann
Reviewed-by:
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
MMIO region in Tdx guest is set with PcdTdxSharedBitMask in TdxDxe's
entry point. In SEV guest the page table entries is set with
PcdPteMemoryEncryptionAddressOrMask when creating 1:1 identity table.
So the AddressEncMask in GetPageTableEnt
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Declare the local variables in SecCoreStartupWithStack that actually
move the data elements as volatile to prevent the optimizer from
replacing this function with the intrinsic memcpy().
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Si
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
If TDX is enabled then we do not support DMA operation in PEI phase.
This is mainly because DMA in TDX guest requires using bounce buffer
(which need to allocate dynamic memory and allocating a PAGE size'd
buffer can be challenge in PEI phas
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
When host VMM create the Td guest, the system memory informations are
stored in TdHob, which is a memory region described in Tdx metadata.
The system memory region in TdHob should be accepted before it can be
accessed. So the newly added fun
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
There are below major changes in this commit.
1. SecEntry.nasm
In TDX BSP and APs goes to the same entry point in SecEntry.nasm.
BSP initialize the temporary stack and then jumps to SecMain, just as
legacy Ovmf does.
APs spin in a modifie
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
Move functions in PlatformPei/Platform.c to PlatformInitLib/Platform.c.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Gerd Hoffmann
Cc: Sebastien Boeuf
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
Move functions in PlatformPei\MemDetect.c to PlatformInitLib\MemDetect.c.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Gerd Hoffmann
Cc: Sebastien Boeu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
MiscInitialization is split into 2 functions:
- PlatformMiscInitialization is for PlatformInitLib.
- MiscInitialization calls PlatformMiscInitialization and then sets
PCD. It is for PlatformPei.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
NoexecDxeInitialization is split into 2 functions:
- PlatformNoexecDxeInitialization is for PlatformInitLib
- NoexecDxeInitialization calls PlatformNoexecDxeInitialization and
then sets PCD.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Br
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
InitializeRamRegions is refactored into 3 calls:
- PlatformQemuInitializeRam
- SevInitializeRam
- PlatformQemuInitializeRamForS3
SevInitializeRam is not in PlatformInitLib. Because in the first stage
PlatformInitLib only support the basic
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
Rename QemuUc32BaseInitialization to PlatformQemuUc32BaseInitialization.
This function is for PlatformInitLib.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
MaxCpuCountInitialization is splitted into two:
- PlatformMaxCpuCountInitialization is for PlatformInitLib
- MaxCpuCountInitialization is for PlatformPei. It calls
PlatformMaxCpuCountInitialization then sets PCDs.
Cc: Ard Biesheuvel
Cc
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
>From this patch we start to restruct the functions which set PCDs into
two, one for PlatformInitLib, one for PlatformPei.
AddressWidthInitialization is the first one. It is splitted into two:
- PlatformAddressWidthInitialization is for Pla
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
Refactor MiscInitialization for CloudHV to set PCD as other platforms
do. Because in the following patch we will split the functions which
set PCDs into two, one for PlatformInitLib, one for PlatformPei.
Cc: Ard Biesheuvel
Cc: Jordan Justen
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
In MiscInitialization Microvm looks a little weird. Other platforms
call PcdSet16S to set the PcdOvmfHostBridgePciDevId with the value same
as PlatformInfoHob->HostBridgeDevId. But Microvm doesn't follow this
way. In switch-case 0x is Mic
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
The intention of PlatformInitLib is to extract the common function used
in OvmfPkg/PlatformPei. This lib will be used not only in PEI phase but
also in SEC phase. SEC phase cannot use global variables between
different functions. So PlatformI
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
In this patch of PlatformInitLib, below hob functions are introduced:
- PlatformAddIoMemoryBaseSizeHob
- PlatformAddIoMemoryRangeHob
- PlatformAddMemoryBaseSizeHob
- PlatformAddMemoryRangeHob
- PlatformAddReservedMemoryBaseSizeHob
They
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
There are 3 variants of PlatformPei in OvmfPkg:
- OvmfPkg/PlatformPei
- OvmfPkg/XenPlatformPei
- OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf
These PlatformPeis can share many common codes, such as
Cmos / Hob / Memory / Platform related funct
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In Tdx BSP may issues commands to APs for some task, for example, to
accept pages paralelly. BSP also need to wait until all the APs have
done the task. TdxMailboxLib wraps these common funtions for BSP.
Cc: Ard Biesheuvel
Cc: Jordan Juste
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
IntelTdx.h defines the defition used by TDX in OvmfPkg:
- Mailbox related defitions,such as the data structure, command code,
AP relocation defitions.
See Table 5.44 Multiprocessor Wakeup Mailbox Structure in below link.
https://uefi.or
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDVF BSP and APs are simplified. BSP is the vCPU-0, while the others
are treated as APs.
So MP intialization is rather simple. The processor info is retrieved by
TDCALL, ApWorker is not supported, BSP is always the working processor,
whi
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add macros CC_GUEST_IS_SEV / CC_GUEST_IS_TDX to check SEV / TDX guest.
Cc: Michael Roth
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Eric Dong
Cc: James Bottomley
Cc: Min Xu
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Jordan Justen
Cc: Ard Biesheuvel
C
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed
directly from/to CPU. Some should be accessed via explicit requests
from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the
help of TdxLib.
Please refer to [TDX
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
This commit supports IoRead/IoWrite for SEV/TDX/Legacy guest in one
binary. It checks the guest type in runtime and then call corresponding
functions.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Brijesh Singh
Cc: Erdem Akta
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Previously IoFifo functions are in X64/IoFifoSev.nasm which supports
both SEV guest and Legacy guest. IoLibFifo.c is introduced to support
SEV/TDX/Legacy guest in one binary. It checks the guest type in runtime
and call corresponding functio
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TDVF access MMIO with TDG.VP.VMCALL to invoke VMM provided emulation
functions. If the access to MMIO fails, it fall backs to the direct
access.
BaseIoLibIntrinsic.inf is the IoLib used by other packages. It will
not support I/O in Td guest
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add base support to handle #VE exceptions. Update the common exception
handlers to invoke the VmTdExitHandleVe () function of the VmgExitLib
library when a #VE is encountered. A non-zero return code will propagate
to the targeted exception h
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Intel TDX architecture does not prescribe a specific software convention
to perform I/O from the guest TD. Guest TD providers have many choices to
provide I/O to the guest. The common I/O models are emulated devices,
para-virtualized devices
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
The base VmgExitLib library provides a default limited interface to
handle #VE exception. To provide full support, the OVMF version of
VmgExitLib is extended to provide full support of #VE handler.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jo
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
VmgExitLib performs the necessary processing to handle a #VC exception.
VmgExitLibNull is a NULL instance of VmgExitLib which provides a
default limited interface. In this commit VmgExitLibNull is extended to
handle a #VE exception with a de
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TdxLib is created with functions to perform the related Tdx operation.
This includes functions for:
- TdAcceptPages : Accept pending private pages and initialize the pages
to all-0 using the TD ephemeral private key.
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Introduce basic Tdx functions in BaseLib:
- TdCall ()
- TdVmCall ()
- TdIsEnabled ()
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: G
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Guest software can be designed to run either as a TD, as a legacy virtual
machine, or directly on the CPU, based on enumeration of its run-time
environment. [TDX-Module] Chap 10.2 defines the flow and the new CPUID
leaf 0x21.
[TDX-Module] A
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3249
Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A T
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Tdx.h includes the Intel Trust Domain Extension definitions.
Detailed information can be found in below document:
https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-module-1eas-v0.85.039.pdf
Cc: Michael D Kinney
Thanks Marvin. That guide is amazing.
As for rebasing, I will get to it once all the old stuff compiles successfully.
Currently, I am working on getting acquainted with tianocore workflow and
migrating everything from cargo-xbuild to build-std feature. Also, some of the
nightly APIs have change
CC Jiewen
(needs whitespace changes cleaned and the bench needs to be rebased beyond 2019
too)
Also see:
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers
Best regards,
Marvin
> On 17. Mar 2022, at 15:54, ayushdevel1...@gmai
Hey Ayush,
I heard Bret likes Rust. :) The Rust staging branch is owned by Jiewen. Nate
handles GSoC. All CC’d (better get used to it fast :) ).
Best regards,
Marvin
> On 16. Mar 2022, at 23:16, ayushdevel1...@gmail.com wrote:
> Hello everyone,
>
> I am Ayush Singh, a 2nd-year student from In
Gentle reminder for PR.
-Original Message-
From: Gao, Zhichao
Sent: Monday, February 21, 2022 1:10 PM
To: Attar, AbdulLateef (Abdul Lateef) ;
devel@edk2.groups.io
Cc: Ni, Ray ; Sami Mujawar
Subject: RE: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser
[CAUTION: Exter
Because it will cause patch to fail in CI test while to succeed if follow the
setting.
Failed test: https://github.com/tianocore/edk2/pull/2535
I guess it's because data structure EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto)
doesn't have /// RSA PSS members in Crypto.c
> -Original Message-
> Fr
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Reviewed-by: Guo Dong
-Original Message-
From: Sean Rhodes
Sent: Thursday, February 24, 2022 12:59 AM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Rhodes, Sean ; Ni,
Ray ; Ma, Maurice ; You, Benjamin
Subject: [PATCH 2/2] UefiPayloadPkg: Hookup SD/MMC timeout
Hook SD_MMC_TIMEOUT build
From: Ayush Singh
Hello everyone,
I am Ayush Singh, an applicant for for GSoC 2022. My Introduction can be found
here ( https://edk2.groups.io/g/devel/message/87637 ).
To get myself acquainted with the project, I was trying to build the Rust tests
in edkii-rust branch in edk2-staging and foun
Hey
Are you following the guideline - don't put new field in the middle ?
ParallelHash256HashAll API is still in the middle..
> @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
>EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT TlsGetHostPublicCert;
>
>EDKII_CRYPTO_TLS_GET_HOS
Good, Thank you Samer.
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Samer El-
> Haj-Mahmoud
> Sent: Thursday, March 17, 2022 9:26 PM
> To: Yao, Jiewen ; Sami Mujawar
> ; Xu, Min M ;
> devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
>
Thanks Sami and Jiewen.
I will bring this to ASWG attention to confirm the change.
> -Original Message-
> From: Yao, Jiewen
> Sent: Thursday, March 17, 2022 9:23 AM
> To: Sami Mujawar ; Xu, Min M
> ; devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
>
Thanks to remind me.
I uploaded version 2 in the same mantis.
Thank you
Yao Jiewen
> -Original Message-
> From: Sami Mujawar
> Sent: Thursday, March 17, 2022 9:10 PM
> To: Yao, Jiewen ; Xu, Min M ;
> devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
>
Hi Jiewen,
I was informed there is an ASWG ECR
https://mantis.uefi.org/mantis/view.php?id=2177 for TDEL. I can see the content
has been approved for ACPI 6.5.
Do you plan to update this ECR to reflect the changes for CCEL or this would be
a separate request?
Regards,
Sami Mujawar
On 10/03/
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Good day,
On 17. Mar 2022, at 02:05, Kuo, Ted wrote:
Hi Liming and Mike,
Can you please review the change?
Thanks,
Ted
-Original Message-
From: devel@edk2.groups.io On Behalf Of Kuo, Ted
Sent: Thursday, March 10, 2022 2:21 PM
To: devel@edk2.groups.io
Cc: Bi, Dandan ; Gao, Liming
Hi Rebecca,
Thank you for this patch. This change looks good to me.
I have a minor suggestion marked inline as [SAMI].
With that upated,
Tested-by: Sami Mujawar
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 05/03/2022 04:19 AM, Rebecca Cran wrote:
Add a RES0 device to the SSDT to res
Hi Rebecca,
I have one minor suggestion marked inline as [SAMI]. Otherwise these
changes look good to me.
With that changed,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 05/03/2022 04:19 AM, Rebecca Cran wrote:
Instead of using a custom Pcd for the ECAM address
(gArmJunoTokenSpaceGu
On March 17, 2022 4:39 PM, Kuo Ted wrote:
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870
> The new algorithm searches FFS3 GUID first and then FFS2 GUID at every 4KB
> address in the top 16MB just below 4GB.
>
> Cc: Ray Ni
> Cc: Debkumar De
> Cc: Harry Han
> Cc: Catharine West
>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870
The new algorithm searches FFS3 GUID first and then FFS2 GUID at
every 4KB address in the top 16MB just below 4GB.
Cc: Ray Ni
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Min Xu
Signed-off-by: Ted Kuo
---
.../Vtf0/Bin/IA32/Rese
Hi, Sami
Thank you for your reviewing, I have created a PR an here is the link.
https://github.com/tianocore/edk2/pull/2619
Regards
Wenyi
On 2022/3/14 18:13, Sami Mujawar wrote:
> Hi Wenyi,
>
> Thank you for this patch. These changes look good to me.
>
> Reviewed-by: Sami Mujawar
>
> Regards
Ted, thank you for the fix in advance!
-Original Message-
From: Kuo, Ted
Sent: Thursday, March 17, 2022 2:05 PM
To: Ni, Ray ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ;
West, Catharine ; Xu, Min M
Subject: RE: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in
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