On March 2, 2022 9:53 AM, Gao Liming wrote:
> Min:
> Is this GUID from
> intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf?
>
> > EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass
> > TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will be
> > in
Reviewed-by: Hao A Wu
Best Regards,
Hao Wu
> -Original Message-
> From: Ma, Hua
> Sent: Thursday, March 3, 2022 1:06 PM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Gao, Liming
> ; Wu, Hao A ; Ni, Ray
> ; Ma, Hua
> Subject: [PATCH v2] MdeModulePkg: Add a check for metadata size in
>
Sorry I missed the earlier feedback from You/Gerd/Jiewen and replied quickly
with my updated patch set. I will try to look at them.
-Vineel
-=-=-=-=-=-=-=-=-=-=-=-
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View/Reply Online (#87252): https://edk2.groups.io/g/devel/message/87
Hi Yi Li,
I am able to incorporate all your feedback regarding commit hygiene. Also able
to validate them by firing an sample PR against EDK2 master
https://github.com/tianocore/edk2/pull/2550/checks
All of the checks passed expected 3 which seems to be infrastructure related. I
would need your
Pushed via:
PR - https://github.com/tianocore/edk2/pull/2574
Commit -
https://github.com/tianocore/edk2/commit/589d51df260465e2561979b8a988e77b0f32a6e8
Best Regards,
Hao Wu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Wu, Hao
> A
> Sent: Wednesday, March 2, 2022 10:10
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
Currently this NvmeExpress Driver do not support metadata handling.
According to the NVME specs, metadata may be transferred to the host after
the logical block data. It can overrun the input buffer which may only
be the size of logical bloc
Any thoughts on this patch, now that the stable tag is out?
> -Original Message-
> From: Ni, Ray
> Sent: Tuesday, February 15, 2022 11:52 PM
> To: Sindhu, Deepthi
> Cc: Wu, Hao A ; Jeff Brasen ;
> devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH v2]
> MdeModulePkg/NonDiscoverableP
The current xhc implementation may exceed the 64K boundary,
so must restrictions need to be added.
Cc: Ray Ni
Cc: Liming Gao
Cc: Wang Jian J
Reviewed-by: Wu Hao A
Signed-off-by: Cheng Zhou
zhoucheng (1):
MdeModulePkg:Avoid Xhc cross 64K boundary
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c |
The current xhc implementation may exceed the 64K boundary,
so must restrictions need to be added.
Cc: Ray Ni
Cc: Liming Gao
Cc: Wang Jian J
Reviewed-by: Wu Hao A
Signed-off-by: Cheng Zhou
---
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/
Hi Min,
Similar to patch 25, I don't see the needs to make this PCD dynamic only.
Do you have any strong reasons? If not sure, maybe it'd be better to put
it under following section.
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
Regards,
Jian
> -Original Message-
Hi Min,
I think the PCD should not be dynamic. Dynamic PCD is used for those features
which can be changed at boot time. But, for Intel processor, it should always
stay as FALSE. So there's no need to make it dynamic. FixedAtBuild should be
fine.
Regards,
Jian
> -Original Message-
> Fro
Thanks for the patch, a couple of inline comments below:
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ma, Hua
> Sent: Thursday, March 3, 2022 10:06 AM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Gao, Liming
> ; Wu, Hao A ; Ni, Ray
> ; Ma, Hua
> Subject: [edk2-devel
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
Currently this NvmeExpress Driver do not support metadata handling.
According to the NVME specs, metadata may be transferred to the host after
the logical block data. It can overrun the input buffer which may only
be the size of logical bloc
Hi Patrik,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 28/02/2022 05:57 PM, patrik.bergl...@arm.com wrote:
From: Patrik Berglund
The definition of macros (e.g. SECURE_BOOT_ENABLE and others) in
ArmVExpress.dsc.inc overrides
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
UefiPayloadPkg\UefiPayloadEntry
Cc: Guo Dong
Cc: Ray Ni
Signed-off-by: Yu Pu
---
UefiPayloadPkg/UefiPayl
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
add the defination of UefiCpuLib in EmulatorPkg\EmulatorPkg.dsc
Cc: Andrew Fish
Cc: Ray Ni
Signed-off-by: Yu Pu
---
EmulatorPkg/EmulatorPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorP
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU
physical address mask calculation and remove the duplicated
code in edk2\IntelFsp2Pkg\Library\BaseCacheLib\CacheLib.c.
Cc: Chasel Chiu
Signed-off-by: Yu Pu
---
IntelFsp2Pkg/L
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
StandaloneMmPkg\Library\StandaloneMmMemLib\X86StandaloneMmMemLibInternal.c
Cc: Ard Biesheuvel
Cc: Sami Mujawa
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
OvmfPkg\XenPlatformPei\MemDetect.c.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Signed-off-by: Yu Pu
---
Ovm
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in MdeModulePkg.
Cc: Jian J Wang
Cc: Liming Gao
Signed-off-by: Yu Pu
---
MdeModulePkg/Core/DxeIplPeim/X64/Vi
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Signed-off-by: Yu Pu
*** BLURB HERE ***
Yu Pu (7):
UefiCpuPackage: Add APIs for CPU physical address mask calculation
MdeModulePkg: Invoke GetPhysicalAddressBits() and remove the
duplicated code
IntelFsp2Pkg: Invoke GetPhysicalAd
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Add API named GetPhysicalAddressBits() for CPU physical address mask
calculation, and remove the duplicated code in UefiCpuPackage.
Cc: Eric Dong
Cc: Ray Ni
Signed-off-by: Yu Pu
---
UefiCpuPkg/CpuDxe/CpuDxe.c |
From: Sebastien Boeuf
Instead of using the CMOS, the CloudHv platform relies on the list of
memmap entries provided through the PVH boot protocol to determine the
last RAM address below 4G.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/PlatformPei/MemDetect.c | 73 +++
From: Sebastien Boeuf
Add some documentation to the CloudHv target in order to clarify how to
use it and what to expect from it.
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/CloudHv/README | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 OvmfP
From: Sebastien Boeuf
Instead of hardcoding the address of the RSDP in the firmware, let's
rely on the PVH structure hvm_start_info to retrieve this information.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 ++
OvmfPkg/AcpiPlatfor
From: Sebastien Boeuf
Following the model from the Xen target, CloudHv is generated as a PVH
ELF binary to take advantage of the PVH specification, which requires
less emulation from the VMM.
The fdf include file CloudHvElfHeader.fdf.inc has been generated from
the following commands:
$ gcc -D
From: Sebastien Boeuf
Instead of having the PVH ELF header part of the fdf file directly, we
move it to a dedicated include file. This is the first step in
automating the generation of the header.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/OvmfXen.fdf | 57 ++-
From: Sebastien Boeuf
CloudHv doesn't need any VARS store, and it doesn't need the CODE
section to be generated separately either. The only thing needed is to
generate a firmware binary that can be used by Cloud Hypervisor.
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/CloudHv/CloudHvX64.fdf | 30
From: Sebastien Boeuf
Updating the fdf include file based on the run of the ELF header
generator. The diff from this patch is the result of:
$ gcc -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c
$ ./elf_gen 2097152 OvmfPkg/XenElfHeader.fdf.inc
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Bo
From: Sebastien Boeuf
Adding some flexibility to the program through optional parameters and
global define, so that other targets can use the generator.
* A global define is added so that we can choose at build time if we
want to use 32-bit or 64-bit base structures.
* A first optional paramet
From: Sebastien Boeuf
Cloud Hypervisor aims at emulating the minimal amount of legacy devices
and this is why the PVH boot specification is supported. The point is to
be able to share some information with the guest without the need for
emulating devices that would be present on real hardware.
S
>From requirement perspective, I am thinking more broadly than just ECC.
Looking at
https://github.com/tianocore/edk2/blob/master/CryptoPkg/Library/Include/openssl/opensslconf.h
today, we disabled lots of thing, ECDH, ECDSA, TLS1_3, which might be
potential useful. While the algorithm we used t
On Wed, 2022-03-02 at 08:17 +0100, Gerd Hoffmann wrote:
> > -[FD.CLOUDHV_VARS]
> > -[FD.CLOUDHV_CODE]
>
> Dropping these two should be a separate patch,
> so this patch becomes more readable.
Sounds good.
>
> > -0x|$(FVMAIN_SIZE)
> > +0x1000|$(FVMAIN_SIZE)
>
> FVMAIN_SIZE is not ch
On Wed, Mar 02, 2022 at 06:59:48AM +, Yao, Jiewen wrote:
> I think another option to pursue is to how to control the openssl
> configuration from module or platform level.
>
> E.g. what if platform-A has enough size and wants to use ECC, while
> platform-B has size constrain and wants to dis
> -[FD.CLOUDHV_VARS]
> -[FD.CLOUDHV_CODE]
Dropping these two should be a separate patch,
so this patch becomes more readable.
> -0x|$(FVMAIN_SIZE)
> +0x1000|$(FVMAIN_SIZE)
FVMAIN_SIZE is not changes anywhere it seems.
So CLOUDHV.fd ends up with some odd size (instead of 2M or 4M) I g
On Tue, Mar 01, 2022 at 02:29:17PM +0100, sebastien.bo...@intel.com wrote:
> From: Sebastien Boeuf
>
> Add some documentation to the CloudHv target in order to clarify how to
> use it and what to expect from it.
>
> Signed-off-by: Sebastien Boeuf
Acked-by: Gerd Hoffmann
-=-=-=-=-=-=-=-=-=-
Hi,
> > Hmm. Unlike patches 17+18 which are pure code motion (except the
> > function renaming but that doesn't change the workflow) this patch mixes
> > code changes and code moving which makes it hard to review.
> >
> > It should be splitted into one (or more) patches changing the functions
On Wed, Mar 02, 2022 at 08:39:28AM +, Kilian Kegel wrote:
> Hi Gerd,
>
> additionally I would suggest once more to adjust the DLINK_FLAGS in
> tools_def.txt to hold CompilerNameINTRIN32/64.LIB as a search library
> as already introduced in
> https://edk2.groups.io/g/devel/message/86072?p=%2C
Hi,
> 2. Jiewen (Cc'ed) suggested to look into using CryptoPkg/Driver instead of
> linking openssl as Library, so we have only one copy of the code. Not
> investigated yet.
>
> Does it means OvmfPkg will use CryptDxe instead of BaseCryptoLib and
> OpensslLib directly? Sounds will be a big c
Thanks Yu!
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Pu, Yu
> Sent: Wednesday, March 2, 2022 5:19 PM
> To: devel@edk2.groups.io
> Cc: Pu, Yu ; Chiu, Chasel
> Subject: [PATCH v1 3/7] IntelFsp2Pkg: Invoke GetPhysicalAddressBits() and
> remove the duplicated code
>
> REF:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.
Some modifications to pass CI test.
Cc: Jiewen Yao
Cc: Jian J Wan
Reviewed-by: Ray Ni
-Original Message-
From: Li, Zhihao
Sent: Tuesday, March 1, 2022 7:22 PM
To: devel@edk2.groups.io
Cc: Dong, Eric ; Ni, Ray ; Kumar, Rahul1
; Fu, Siyuan
Subject: [PATCH v5 1/1] UefiCpuPkg: Extend SMM CPU Service with rendezvous
support.
REF： https://bugzilla.tiano
QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.
Signed-off-by: xianglai li
---
.../Include/IndustryStandard/QemuFwCfg.h | 95
.../Include
This library provides interfaces such as
real-time clock initialization
to get time and setting time.
Signed-off-by: xianglai li
---
.../LsRealTimeClockLib/LsRealTimeClock.h | 41 +++
.../LsRealTimeClockLib/LsRealTimeClockLib.c | 343 ++
.../LsRealTimeClockLib/LsRealTimeC
The Library provides Boot Manager interfaces.
Signed-off-by: xianglai li
---
.../PlatformBootManagerLib/PlatformBm.c | 761 ++
.../PlatformBootManagerLib/PlatformBm.h | 126 +++
.../PlatformBootManagerLib.inf| 78 ++
.../PlatformBootManagerLib/QemuKer
Support Dxe for LoogArch.
Signed-off-by: xianglai li
---
.../Loongson/LoongArchQemuPkg/Loongson.dec| 14 +-
.../Loongson/LoongArchQemuPkg/Loongson.dsc| 385 +-
.../Loongson/LoongArchQemuPkg/Loongson.fdf| 241 +++
.../LoongArchQemuPkg/Loongson.fdf.inc
Platform PEI module for LoongArch platform initialization.
Signed-off-by: xianglai li
---
.../Loongson/LoongArchQemuPkg/Loongson.dec| 22 ++
.../Loongson/LoongArchQemuPkg/Loongson.dsc| 66 -
.../Loongson/LoongArchQemuPkg/Loongson.fdf| 51
.../LoongArchQemuPkg/PlatformPei/
The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c | 382 ++
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h | 153 +++
.../Drivers/CpuDxe/CpuDxe.inf |
This library provides interfaces related to restart and shutdown.
Signed-off-by: xianglai li
---
.../Library/ResetSystemLib/ResetSystemLib.c | 155 ++
.../Library/ResetSystemLib/ResetSystemLib.inf | 40 +
2 files changed, 195 insertions(+)
create mode 100644
Platform/Loo
Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.
Signed-off-by: xianglai li
---
.../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 548 ++
Read the memory map information through the QemuFwCfg interface,
then build the page table through the memory map information,
and finally enable Mmu.
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Include/Library/MmuLib.h | 85 ++
.../LoongArchQemuPkg/Library/MmuLib/Mmu.S | 35 +
...
This library provides interfaces for creating kernel boot parameters.
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Include/Library/Bpi.h| 77 +++
.../LoongArchQemuPkg/Library/BpiLib/Bpi.c | 492 ++
.../Library/BpiLib/BpiLib.inf | 38 ++
3 files ch
The uploaded code generates firmware to support Linux launching on the
LoongArch platform under qemu,
So it will run in a virtual machine.
LoongArch is the general processor architecture of Loongson.
You can get the latest LoongArch documents or LoongArch tools at
https://github.com/loongson/.
Add SEC Code And Readme.md for LoongArchQemu
Signed-off-by: xianglai li
Signed-off-by: xianglai li
---
.../Include/LoongArchAsmMacro.h | 23 +
.../Loongson/LoongArchQemuPkg/Loongson.dec| 38 ++
.../Loongson/LoongArchQemuPkg/Loongson.dsc| 133 +
.../Loongson/LoongArc
This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.
Signed-off-by: xianglai li
---
.../Drivers/StableTimerDxe/Timer.c| 405 ++
.../Drivers/StableTimerDxe/Timer.h| 166 +++
.../Drivers/StableTimerDxe
This library provides a delay interface and a timing interface.
Signed-off-by: xianglai li
---
.../Include/Library/StableTimer.h | 42 +++
.../Library/StableTimerLib/Count.S| 26 ++
.../Library/StableTimerLib/TimerLib.c | 262 ++
.../Library/Stab
Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.
Signed-off-by: xianglai li
---
.../PeiServicesTablePointer.c | 78 +++
.../PeiServicesTablePointerLib.inf| 32
2 files c
Serial Port library for LoongarchQemuPkg
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Include/Library/Cpu.h| 344 ++
.../Include/LoongArchQemuPlatform.h | 103 +++
.../Library/SerialPortLib/SerialPortLib.c | 614 ++
.../Library/SerialPortLib/Seria
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.
Some modifications to pass CI test.
Cc: Jiewen Yao
Cc: Jian J Wan
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